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-rw-r--r--configs/dram/lat_mem_rd.py6
-rw-r--r--configs/dram/sweep.py4
2 files changed, 5 insertions, 5 deletions
diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index 374f1d4be..d4015a522 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -44,8 +44,8 @@ from m5.objects import *
from m5.util import addToPath
from m5.internal.stats import periodicStatDump
-addToPath('../common')
-import MemConfig
+addToPath('../')
+from common import MemConfig
addToPath('../../util')
import protolib
@@ -258,7 +258,7 @@ system.tgen.port = system.monitor.slave
# create the actual cache hierarchy, for now just go with something
# basic to explore some of the options
-from Caches import *
+from common.Caches import *
# a starting point for an L3 cache
class L3Cache(Cache):
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 368e39488..2797abef0 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -42,9 +42,9 @@ from m5.objects import *
from m5.util import addToPath
from m5.internal.stats import periodicStatDump
-addToPath('../common')
+addToPath('../')
-import MemConfig
+from common import MemConfig
# this script is helpful to sweep the efficiency of a specific memory
# controller configuration, by varying the number of banks accessed,