diff options
Diffstat (limited to 'configs/example/ruby_mem_test.py')
| -rw-r--r-- | configs/example/ruby_mem_test.py | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index b164447f8..7848a8672 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -108,7 +108,8 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), funcbus = NoncoherentBus(), physmem = SimpleMemory(), - clk_domain = SrcClockDomain(clock = options.sys_clock)) + clk_domain = SrcClockDomain(clock = options.sys_clock), + mem_ranges = [AddrRange(options.mem_size)]) if options.num_dmas > 0: dmas = [ MemTest(atomic = False, @@ -129,8 +130,13 @@ for (i, dma) in enumerate(dmas): dma_ports.append(dma.test) Ruby.create_system(options, system, dma_ports = dma_ports) +# Create a top-level voltage domain and clock domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) # Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) # # The tester is most effective when randomization is turned on and @@ -183,6 +189,6 @@ m5.ticks.setGlobalFrequency('1ns') m5.instantiate() # simulate until program terminates -exit_event = m5.simulate(options.maxtick) +exit_event = m5.simulate(options.abs_max_tick) print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |