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-rw-r--r--configs/example/se.py20
1 files changed, 3 insertions, 17 deletions
diff --git a/configs/example/se.py b/configs/example/se.py
index 83c2b1f8d..0a158244f 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -41,10 +41,6 @@ from Caches import *
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
m5_root = os.path.dirname(config_root)
-print m5_root
-print config_path
-print config_root
-
parser = optparse.OptionParser()
@@ -92,16 +88,7 @@ if options.detailed:
process += [smt_process, ]
smt_idx += 1
-
-if options.timing:
- CPUClass = TimingSimpleCPU
- test_mem_mode = 'timing'
-elif options.detailed:
- CPUClass = DerivO3CPU
- test_mem_mode = 'timing'
-else:
- CPUClass = AtomicSimpleCPU
- test_mem_mode = 'atomic'
+(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
CPUClass.clock = '2GHz'
@@ -114,13 +101,12 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
system.physmem.port = system.membus.port
for i in xrange(np):
- if options.caches and not options.standard_switch:
+ if options.caches and not options.standard_switch and not FutureClass:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
system.cpu[i].connectMemPorts(system.membus)
- system.cpu[i].mem = system.physmem
system.cpu[i].workload = process
root = Root(system = system)
-Simulation.run(options, root, system)
+Simulation.run(options, root, system, FutureClass)