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-rw-r--r--configs/example/memtest.py2
-rw-r--r--configs/example/se.py2
2 files changed, 2 insertions, 2 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 2dcccbba6..590378920 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -148,7 +148,7 @@ def make_level(spec, prototypes, attach_obj, attach_port):
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = Bus(clock="500MHz", width=16)
+ new_bus = CoherentBus(clock="500MHz", width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff --git a/configs/example/se.py b/configs/example/se.py
index 8324bea4e..83abbd2f3 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -153,7 +153,7 @@ np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = SimpleMemory(range=AddrRange("512MB")),
- membus = Bus(), mem_mode = test_mem_mode)
+ membus = CoherentBus(), mem_mode = test_mem_mode)
# Sanity check
if options.fastmem and (options.caches or options.l2cache):