diff options
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 1 | ||||
| -rw-r--r-- | configs/example/memtest.py | 138 |
2 files changed, 139 insertions, 0 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 3573c47ac..11b82178b 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -95,6 +95,7 @@ class MyCache(BaseCache): latency = 1 mshrs = 10 tgts_per_mshr = 5 + protocol = CoherenceProtocol(protocol='moesi') # driver system CPU is always simple... note this is an assignment of # a class, not an instance. diff --git a/configs/example/memtest.py b/configs/example/memtest.py new file mode 100644 index 000000000..141ecfd8e --- /dev/null +++ b/configs/example/memtest.py @@ -0,0 +1,138 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * +import os, optparse, sys +m5.AddToPath('../common') + +parser = optparse.OptionParser() + +parser.add_option("--caches", action="store_true") +parser.add_option("-t", "--timing", action="store_true") +parser.add_option("-m", "--maxtick", type="int") +parser.add_option("-l", "--maxloads", default = "1000000000000", type="int") +parser.add_option("-n", "--numtesters", default = "8", type="int") +parser.add_option("-p", "--protocol", + default="moesi", + help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)") + +(options, args) = parser.parse_args() + +if args: + print "Error: script doesn't take any positional arguments" + sys.exit(1) + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 12 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol=options.protocol) + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 10 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#MAX CORES IS 8 with the false sharing method +if options.numtesters > 8: + print "Error: NUmber of testers limited to 8 because of false sharing" + sys,exit(1) + +if options.timing: + cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, + percent_uncacheable=10, progress_interval=1000) + for i in xrange(options.numtesters) ] +else: + cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, + percent_uncacheable=10, progress_interval=1000) + for i in xrange(options.numtesters) ] +# system simulated +system = System(cpu = cpus, funcmem = PhysicalMemory(), + physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16)) + +# l2cache & bus +if options.caches: + system.toL2Bus = Bus(clock="500GHz", width=16) + system.l2c = L2(size='64kB', assoc=8) + system.l2c.cpu_side = system.toL2Bus.port + + # connect l2c to membus + system.l2c.mem_side = system.membus.port + +which_port = 0 +# add L1 caches +for cpu in cpus: + if options.caches: + cpu.l1c = L1(size = '32kB', assoc = 4) + cpu.test = cpu.l1c.cpu_side + cpu.l1c.mem_side = system.toL2Bus.port + else: + cpu.test = system.membus.port + if which_port == 0: + system.funcmem.port = cpu.functional + which_port = 1 + else: + system.funcmem.functional = cpu.functional + + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +if options.timing: + root.system.mem_mode = 'timing' +else: + root.system.mem_mode = 'atomic' + +# instantiate configuration +m5.instantiate(root) + +# simulate until program terminates +if options.maxtick: + exit_event = m5.simulate(options.maxtick) +else: + exit_event = m5.simulate() + +print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() |