diff options
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/memtest.py | 4 | ||||
| -rw-r--r-- | configs/example/ruby_mem_test.py | 2 | ||||
| -rw-r--r-- | configs/example/se.py | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/configs/example/memtest.py b/configs/example/memtest.py index feeffa764..eaf3a52bd 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -147,7 +147,7 @@ for scale in treespec[:-2]: # system simulated system = System(funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), + funcbus = NoncoherentXBar(), physmem = SimpleMemory(latency = "100ns"), cache_line_size = block_size) @@ -162,7 +162,7 @@ def make_level(spec, prototypes, attach_obj, attach_port): parent = attach_obj # use attach obj as config parent too if len(spec) > 1 and (fanout > 1 or options.force_bus): port = getattr(attach_obj, attach_port) - new_bus = CoherentBus(width=16) + new_bus = CoherentXBar(width=16) if (port.role == 'MASTER'): new_bus.slave = port attach_port = "master" diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index 99f6f4a09..4e2cde791 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -106,7 +106,7 @@ cpus = [ MemTest(atomic = False, system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), + funcbus = NoncoherentXBar(), physmem = SimpleMemory(), clk_domain = SrcClockDomain(clock = options.sys_clock), mem_ranges = [AddrRange(options.mem_size)]) diff --git a/configs/example/se.py b/configs/example/se.py index 8ec90599b..f5aef5c2f 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -255,7 +255,7 @@ if options.ruby: system.cpu[i].dtb.walker.port = ruby_port.slave else: MemClass = Simulation.setMemClass(options) - system.membus = CoherentBus() + system.membus = CoherentXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) |