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-rw-r--r--configs/example/fs.py24
-rw-r--r--configs/example/memtest.py4
-rw-r--r--configs/example/ruby_direct_test.py8
-rw-r--r--configs/example/ruby_fs.py12
-rw-r--r--configs/example/ruby_mem_test.py7
-rw-r--r--configs/example/ruby_network_test.py7
-rw-r--r--configs/example/ruby_random_test.py7
-rw-r--r--configs/example/se.py15
8 files changed, 59 insertions, 25 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index cbcacd6d4..028148404 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010-2012 ARM Limited
+# Copyright (c) 2010-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -81,9 +81,6 @@ def is_kvm_cpu(cpu_class):
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-TestCPUClass.clock = options.cpu_clock
-DriveCPUClass.clock = options.cpu_clock
-
# Match the memories with the CPUs, the driver system always simple,
# and based on the options for the test system
DriveMemClass = SimpleMemory
@@ -120,7 +117,11 @@ elif buildEnv['TARGET_ISA'] == "arm":
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
-test_sys.clock = options.sys_clock
+# Create a source clock for the system and set the clock period
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+
+# Create a source clock for the CPUs and set the clock period
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
@@ -130,7 +131,9 @@ if options.script is not None:
test_sys.init_param = options.init_param
-test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
+# For now, assign all the CPUs to the same clock domain
+test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
+ for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
@@ -174,9 +177,14 @@ if len(bm) == 2:
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
DriveMemClass, bm[1])
- drive_sys.clock = options.sys_clock
+ # Create a source clock for the system and set the clock period
+ drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+
+ # Create a source clock for the CPUs and set the clock period
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
- drive_sys.cpu = DriveCPUClass(cpu_id=0)
+ drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
+ cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index e8dc52fb5..a74f4b2f3 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -144,14 +144,14 @@ for scale in treespec[:-2]:
system = System(funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = CoherentBus(clock="500MHz", width=16)
+ new_bus = CoherentBus(width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index a60725230..e4d4c73f8 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -92,8 +92,9 @@ else:
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
#
# Create the ruby random tester
#
@@ -103,6 +104,9 @@ system.tester = RubyDirectedTester(requests_to_complete = \
Ruby.create_system(options, system)
+# Since Ruby runs at an independent frequency, create a seperate clock
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for ruby_port in system.ruby._cpu_ruby_ports:
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 403e55584..a1293a08c 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -80,8 +80,6 @@ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
sys.exit(1)
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
-
TestMemClass = Simulation.setMemClass(options)
if buildEnv['TARGET_ISA'] == "alpha":
@@ -93,7 +91,7 @@ elif buildEnv['TARGET_ISA'] == "x86":
else:
fatal("incapable of building non-alpha or non-x86 full system!")
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
if options.kernel is not None:
system.kernel = binary(options.kernel)
@@ -102,12 +100,20 @@ if options.script is not None:
system.readfile = options.script
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
+
+# Create a source clock for the CPUs and set the clock period
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
Ruby.create_system(options, system, system.piobus, system._dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
+ cpu.clk_domain = system.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 14db9d40b..b164447f8 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -107,8 +107,8 @@ cpus = [ MemTest(atomic = False,
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
@@ -129,6 +129,9 @@ for (i, dma) in enumerate(dmas):
dma_ports.append(dma.test)
Ruby.create_system(options, system, dma_ports = dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index 74bdd5504..b6fdc416f 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -104,11 +104,14 @@ cpus = [ NetworkTest(fixed_pkts=options.fixed_pkts,
# create the desired simulated system
system = System(cpu = cpus,
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
i = 0
for ruby_port in system.ruby._cpu_ruby_ports:
#
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 646863e88..cd1b82f16 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -97,11 +97,14 @@ tester = RubyTester(check_flush = check_flush,
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(tester = tester, physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(tester = tester, physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
tester.num_cpus = len(system.ruby._cpu_ruby_ports)
diff --git a/configs/example/se.py b/configs/example/se.py
index 3ff3f0c7d..a564901a3 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -147,7 +147,6 @@ else:
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
CPUClass.numThreads = numThreads
MemClass = Simulation.setMemClass(options)
@@ -159,8 +158,16 @@ if options.smt and options.num_cpus > 1:
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange("512MB")),
- mem_mode = test_mem_mode)
-system.clock = options.sys_clock
+ mem_mode = test_mem_mode,
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
+# Create a separate clock domain for the CPUs
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
+# All cpus belong to a common cpu_clk_domain, therefore running at a common
+# frequency.
+for cpu in system.cpu:
+ cpu.clk_domain = system.cpu_clk_domain
# Sanity check
if options.fastmem:
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 18:45:13 +0000