diff options
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 24 | ||||
| -rw-r--r-- | configs/example/se.py | 29 |
2 files changed, 28 insertions, 25 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 05e35c4ba..08484559a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -1,4 +1,4 @@ -# Copyright (c) 2010 ARM Limited +# Copyright (c) 2010-2011 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -157,23 +157,19 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] CacheConfig.config_cache(options, test_sys) +if bm[0]: + mem_size = bm[0].mem() +else: + mem_size = SysConfig().mem() if options.caches or options.l2cache: - if bm[0]: - mem_size = bm[0].mem() - else: - mem_size = SysConfig().mem() - # For x86, we need to poke a hole for interrupt messages to get back to the - # CPU. These use a portion of the physical address space which has a - # non-zero prefix in the top nibble. Normal memory accesses have a 0 - # prefix. - if buildEnv['TARGET_ISA'] == 'x86': - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)] - else: - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] - test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] test_sys.iocache = IOCache(addr_range=mem_size) test_sys.iocache.cpu_side = test_sys.iobus.port test_sys.iocache.mem_side = test_sys.membus.port +else: + test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', + ranges = [AddrRange(mem_size)]) + test_sys.iobridge.slave = test_sys.iobus.port + test_sys.iobridge.master = test_sys.membus.port for i in xrange(np): if options.fastmem: diff --git a/configs/example/se.py b/configs/example/se.py index 56737d6d5..572364482 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2008 The Regents of The University of Michigan # All rights reserved. # @@ -152,20 +164,13 @@ if options.cpu_type == "detailed" or options.cpu_type == "inorder": process += [smt_process, ] smt_idx += 1 numThreads = len(workloads) - + if options.ruby: - if options.cpu_type == "detailed": - print >> sys.stderr, "Ruby only works with TimingSimpleCPU!!" + if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): + print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) - elif not options.cpu_type == "timing": - print >> sys.stderr, "****WARN: using Timing CPU since it's needed by Ruby" - - class CPUClass(TimingSimpleCPU): pass - test_mem_mode = 'timing' - FutureClass = None -else: - (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) +(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) CPUClass.clock = '2GHz' CPUClass.numThreads = numThreads; @@ -179,7 +184,9 @@ if options.ruby: options.use_map = True Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) + system.system_port = system.ruby._sys_port_proxy.port else: + system.system_port = system.membus.port system.physmem.port = system.membus.port CacheConfig.config_cache(options, system) |