diff options
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 38 | ||||
| -rw-r--r-- | configs/example/ruby_fs.py | 13 |
2 files changed, 35 insertions, 16 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 028148404..037a54b75 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -102,17 +102,16 @@ else: np = options.num_cpus if buildEnv['TARGET_ISA'] == "alpha": - test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0]) + test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "mips": - test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0]) + test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "sparc": - test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0]) + test_sys = makeSparcSystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "x86": - test_sys = makeLinuxX86System(test_mem_mode, TestMemClass, - options.num_cpus, bm[0]) + test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) elif buildEnv['TARGET_ISA'] == "arm": - test_sys = makeArmSystem(test_mem_mode, options.machine_type, - TestMemClass, bm[0], options.dtb_filename, + test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], + options.dtb_filename, bare_metal=options.bare_metal) else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) @@ -164,18 +163,24 @@ for i in xrange(np): CacheConfig.config_cache(options, test_sys) +# Create the appropriate memory controllers and connect them to the +# memory bus +test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True) + for r in test_sys.mem_ranges] +for i in xrange(len(test_sys.mem_ctrls)): + test_sys.mem_ctrls[i].port = test_sys.membus.master + if len(bm) == 2: if buildEnv['TARGET_ISA'] == 'alpha': - drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1]) + drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) elif buildEnv['TARGET_ISA'] == 'mips': - drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1]) + drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) elif buildEnv['TARGET_ISA'] == 'sparc': - drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1]) + drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) elif buildEnv['TARGET_ISA'] == 'x86': - drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1]) + drive_sys = makeX86System(drive_mem_mode, np, bm[1]) elif buildEnv['TARGET_ISA'] == 'arm': - drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, - DriveMemClass, bm[1]) + drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) # Create a source clock for the system and set the clock period drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) @@ -201,6 +206,13 @@ if len(bm) == 2: drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave + # Create the appropriate memory controllers and connect them to the + # memory bus + drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True) + for r in drive_sys.mem_ranges] + for i in xrange(len(drive_sys.mem_ctrls)): + drive_sys.mem_ctrls[i].port = drive_sys.membus.master + drive_sys.init_param = options.init_param root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) elif len(bm) == 1: diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index a1293a08c..a254841d2 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -83,10 +83,9 @@ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): TestMemClass = Simulation.setMemClass(options) if buildEnv['TARGET_ISA'] == "alpha": - system = makeLinuxAlphaRubySystem(test_mem_mode, TestMemClass, bm[0]) + system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) elif buildEnv['TARGET_ISA'] == "x86": - system = makeLinuxX86System(test_mem_mode, TestMemClass, - options.num_cpus, bm[0], True) + system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) Simulation.setWorkCountOptions(system, options) else: fatal("incapable of building non-alpha or non-x86 full system!") @@ -127,5 +126,13 @@ for (i, cpu) in enumerate(system.cpu): system.ruby._cpu_ruby_ports[i].access_phys_mem = True +# Create the appropriate memory controllers and connect them to the +# PIO bus +system.mem_ctrls = [TestMemClass(range = r, + conf_table_reported = True) + for r in system.mem_ranges] +for i in xrange(len(system.physmem)): + system.mem_ctrls[i].port = system.piobus.master + root = Root(full_system = True, system = system) Simulation.run(options, root, system, FutureClass) |