summaryrefslogtreecommitdiff
path: root/configs/example
diff options
context:
space:
mode:
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/fs.py23
-rw-r--r--configs/example/se.py15
2 files changed, 33 insertions, 5 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 037a54b75..ff59ca67d 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -116,11 +116,20 @@ elif buildEnv['TARGET_ISA'] == "arm":
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
+# Create a top-level voltage domain
+test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
-test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = test_sys.voltage_domain)
+
+# Create a CPU voltage domain
+test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
-test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ test_sys.cpu_voltage_domain)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
@@ -182,11 +191,19 @@ if len(bm) == 2:
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
+ # Create a top-level voltage domain
+ drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
# Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+ # Create a CPU voltage domain
+ drive_sys.cpu_voltage_domain = VoltageDomain()
+
# Create a source clock for the CPUs and set the clock period
- drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ drive_sys.cpu_voltage_domain)
drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
cpu_id=0)
diff --git a/configs/example/se.py b/configs/example/se.py
index 7b577239f..39572cd86 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -159,11 +159,22 @@ np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange(options.mem_size)),
mem_mode = test_mem_mode,
- clk_domain = SrcClockDomain(clock = options.sys_clock),
cache_line_size = options.cacheline_size)
+# Create a top-level voltage domain
+system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
+
+# Create a source clock for the system and set the clock period
+system.clk_domain = SrcClockDomain(clock = options.sys_clock,
+ voltage_domain = system.voltage_domain)
+
+# Create a CPU voltage domain
+system.cpu_voltage_domain = VoltageDomain()
+
# Create a separate clock domain for the CPUs
-system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
+ voltage_domain =
+ system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.