diff options
Diffstat (limited to 'configs/example')
| -rw-r--r-- | configs/example/fs.py | 1 | ||||
| -rw-r--r-- | configs/example/memtest.py | 34 | ||||
| -rw-r--r-- | configs/example/se.py | 11 |
3 files changed, 23 insertions, 23 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index bd4637e95..76c12bd9e 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -51,7 +51,6 @@ parser.add_option("--kernel", action="store", type="string") parser.add_option("--script", action="store", type="string") # Benchmark options -parser.add_option("--l2cache", action="store_true") parser.add_option("--dual", action="store_true", help="Simulate two systems attached with an ethernet link") parser.add_option("-b", "--benchmark", action="store", type="string", diff --git a/configs/example/memtest.py b/configs/example/memtest.py index e42a92ba1..c28ffab10 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ if args: # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -65,7 +65,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -75,28 +75,24 @@ if options.numtesters > 8: print "Error: NUmber of testers limited to 8 because of false sharing" sys,exit(1) -if options.timing: - cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, - percent_uncacheable=10, progress_interval=1000) - for i in xrange(options.numtesters) ] -else: - cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, - percent_uncacheable=10, progress_interval=1000) - for i in xrange(options.numtesters) ] +cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads, + percent_functional=50, percent_uncacheable=10, + progress_interval=1000) + for i in xrange(options.numtesters) ] + # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16)) + physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16)) # l2cache & bus if options.caches: - system.toL2Bus = Bus(clock="500GHz", width=16) + system.toL2Bus = Bus(clock="500MHz", width=16) system.l2c = L2(size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port -which_port = 0 # add L1 caches for cpu in cpus: if options.caches: @@ -105,12 +101,7 @@ for cpu in cpus: cpu.l1c.mem_side = system.toL2Bus.port else: cpu.test = system.membus.port - if which_port == 0: - system.funcmem.port = cpu.functional - which_port = 1 - else: - system.funcmem.functional = cpu.functional - + system.funcmem.port = cpu.functional # connect memory to membus system.physmem.port = system.membus.port @@ -126,6 +117,9 @@ if options.timing: else: root.system.mem_mode = 'atomic' +# Not much point in this being higher than the L1 latency +m5.ticks.setGlobalFrequency('1ns') + # instantiate configuration m5.instantiate(root) diff --git a/configs/example/se.py b/configs/example/se.py index 0944a030e..b294480f6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -104,7 +104,14 @@ for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - system.cpu[i].connectMemPorts(system.membus) + if options.l2cache: + system.l2 = L2Cache(size='2MB') + system.tol2bus = Bus() + system.l2.cpu_side = system.tol2bus.port + system.l2.mem_side = system.membus.port + system.cpu[i].connectMemPorts(system.tol2bus) + else: + system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process root = Root(system = system) |