summaryrefslogtreecommitdiff
path: root/configs/example
diff options
context:
space:
mode:
Diffstat (limited to 'configs/example')
-rw-r--r--configs/example/memcheck.py4
-rw-r--r--configs/example/memtest.py4
-rw-r--r--configs/example/ruby_mem_test.py2
-rw-r--r--configs/example/se.py2
4 files changed, 6 insertions, 6 deletions
diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py
index 4f85223d9..f0bc26e32 100644
--- a/configs/example/memcheck.py
+++ b/configs/example/memcheck.py
@@ -243,7 +243,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
if level != 0:
# Create a crossbar and add it to the subsystem, note that
# we do this even with a single element on this level
- xbar = CoherentXBar(width = 32)
+ xbar = L2XBar(width = 32)
subsys.xbar = xbar
if next_cache:
xbar.master = next_cache.cpu_side
@@ -269,7 +269,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
if ntesters > 1:
# Create a crossbar and add it to the subsystem
- xbar = CoherentXBar(width = 32)
+ xbar = L2XBar(width = 32)
subsys.xbar = xbar
xbar.master = next_cache.cpu_side
for tester, checker in zip(testers, checkers):
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 6c1e657e4..9a66320d8 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -233,7 +233,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
if level != 0:
# Create a crossbar and add it to the subsystem, note that
# we do this even with a single element on this level
- xbar = CoherentXBar(width = 32)
+ xbar = L2XBar()
subsys.xbar = xbar
if next_cache:
xbar.master = next_cache.cpu_side
@@ -258,7 +258,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
if ntesters > 1:
# Create a crossbar and add it to the subsystem
- xbar = CoherentXBar(width = 32)
+ xbar = L2XBar()
subsys.xbar = xbar
xbar.master = next_cache.cpu_side
for tester in testers:
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index f5e6d2a82..e2887410f 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -106,7 +106,7 @@ cpus = [ MemTest(atomic = False,
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentXBar(),
+ funcbus = IOXBar(),
clk_domain = SrcClockDomain(clock = options.sys_clock),
mem_ranges = [AddrRange(options.mem_size)])
diff --git a/configs/example/se.py b/configs/example/se.py
index 3f51acdeb..a582d2976 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -265,7 +265,7 @@ if options.ruby:
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
- system.membus = CoherentXBar()
+ system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)