summaryrefslogtreecommitdiff
path: root/configs/learning_gem5/part1/two_level.py
diff options
context:
space:
mode:
Diffstat (limited to 'configs/learning_gem5/part1/two_level.py')
-rw-r--r--configs/learning_gem5/part1/two_level.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py
index 878baa312..3dcb71a51 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -128,7 +128,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86":
system.system_port = system.membus.slave
# Create a DDR3 memory controller
-system.mem_ctrl = DDR3_1600_x64()
+system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master