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-rw-r--r--configs/learning_gem5/part1/two_level.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py
index edaeafe79..de012b30e 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -120,9 +120,9 @@ system.cpu.createInterruptController()
# For x86 only, make sure the interrupts are connected to the memory
# Note: these are directly connected to the memory bus and are not cached
if m5.defines.buildEnv['TARGET_ISA'] == "x86":
- system.cpu.interrupts.pio = system.membus.master
- system.cpu.interrupts.int_master = system.membus.slave
- system.cpu.interrupts.int_slave = system.membus.master
+ system.cpu.interrupts[0].pio = system.membus.master
+ system.cpu.interrupts[0].int_master = system.membus.slave
+ system.cpu.interrupts[0].int_slave = system.membus.master
# Connect the system up to the membus
system.system_port = system.membus.slave