diff options
Diffstat (limited to 'configs/learning_gem5')
| -rw-r--r-- | configs/learning_gem5/part1/simple.py | 2 | ||||
| -rw-r--r-- | configs/learning_gem5/part1/two_level.py | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 1249a8464..393240a66 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -75,7 +75,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.cpu.interrupts[0].int_slave = system.membus.master # Create a DDR3 memory controller and connect it to the membus -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py index 878baa312..3dcb71a51 100644 --- a/configs/learning_gem5/part1/two_level.py +++ b/configs/learning_gem5/part1/two_level.py @@ -128,7 +128,7 @@ if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.system_port = system.membus.slave # Create a DDR3 memory controller -system.mem_ctrl = DDR3_1600_x64() +system.mem_ctrl = DDR3_1600_8x8() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master |