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Diffstat (limited to 'configs/ruby/MESI_CMP_directory.py')
-rw-r--r--configs/ruby/MESI_CMP_directory.py14
1 files changed, 14 insertions, 0 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 2f7faab52..4bd969be5 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -71,6 +71,8 @@ def create_system(options, system, piobus, dma_devices):
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
+ cntrl_count = 0
+
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
@@ -92,6 +94,7 @@ def create_system(options, system, piobus, dma_devices):
cpu_seq.pio_port = piobus.port
l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
@@ -104,6 +107,8 @@ def create_system(options, system, piobus, dma_devices):
#
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+
+ cntrl_count += 1
l2_index_start = block_size_bits + l2_bits
@@ -116,11 +121,14 @@ def create_system(options, system, piobus, dma_devices):
start_index_bit = l2_index_start)
l2_cntrl = L2Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
L2cacheMemory = l2_cache)
exec("system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ cntrl_count += 1
+
phys_mem_size = long(system.physmem.range.second) - \
long(system.physmem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
@@ -136,6 +144,7 @@ def create_system(options, system, piobus, dma_devices):
dir_size.value = mem_module_size
dir_cntrl = Directory_Controller(version = i,
+ cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory(version = i,
size = \
@@ -145,6 +154,8 @@ def create_system(options, system, piobus, dma_devices):
exec("system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ cntrl_count += 1
+
for i, dma_device in enumerate(dma_devices):
#
# Create the Ruby objects associated with the dma controller
@@ -154,6 +165,7 @@ def create_system(options, system, piobus, dma_devices):
physmem = system.physmem)
dma_cntrl = DMA_Controller(version = i,
+ cntrl_id = cntrl_count,
dma_sequencer = dma_seq)
exec("system.dma_cntrl%d = dma_cntrl" % i)
@@ -163,6 +175,8 @@ def create_system(options, system, piobus, dma_devices):
exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ cntrl_count += 1
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \