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-rw-r--r--configs/ruby/MI_example.py37
1 files changed, 22 insertions, 15 deletions
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 6f28c6ade..24b0f9716 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -74,21 +74,28 @@ def create_system(options, full_system, system, dma_ports, ruby_system):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
- #
- # Only one unified L1 cache exists. Can cache instructions and data.
- #
- l1_cntrl = L1Cache_Controller(version = i,
- cacheMemory = cache,
- send_evictions = send_evicts(options),
- transitions_per_cycle = options.ports,
- clk_domain=system.cpu[i].clk_domain,
- ruby_system = ruby_system)
-
- cpu_seq = RubySequencer(version = i,
- icache = cache,
- dcache = cache,
- clk_domain=system.cpu[i].clk_domain,
- ruby_system = ruby_system)
+
+ # the ruby random tester reuses num_cpus to specify the
+ # number of cpu ports connected to the tester object, which
+ # is stored in system.cpu. because there is only ever one
+ # tester object, num_cpus is not necessarily equal to the
+ # size of system.cpu; therefore if len(system.cpu) == 1
+ # we use system.cpu[0] to set the clk_domain, thereby ensuring
+ # we don't index off the end of the cpu list.
+ if len(system.cpu) == 1:
+ clk_domain = system.cpu[0].clk_domain
+ else:
+ clk_domain = system.cpu[i].clk_domain
+
+ # Only one unified L1 cache exists. Can cache instructions and data.
+ l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache,
+ send_evictions=send_evicts(options),
+ transitions_per_cycle=options.ports,
+ clk_domain=clk_domain,
+ ruby_system=ruby_system)
+
+ cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
+ clk_domain=clk_domain, ruby_system=ruby_system)
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)