summaryrefslogtreecommitdiff
path: root/configs/ruby/MI_example.py
diff options
context:
space:
mode:
Diffstat (limited to 'configs/ruby/MI_example.py')
-rw-r--r--configs/ruby/MI_example.py11
1 files changed, 6 insertions, 5 deletions
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 5f5703d4e..5018f2c18 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -78,20 +78,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists