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-rw-r--r--configs/ruby/MOESI_hammer.py12
1 files changed, 0 insertions, 12 deletions
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 819834f56..47e37de30 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -81,8 +81,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
#
block_size_bits = int(math.log(options.cacheline_size, 2))
- cntrl_count = 0
-
for i in xrange(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
@@ -99,7 +97,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
start_index_bit = block_size_bits)
l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
L1Icache = l1i_cache,
L1Dcache = l1d_cache,
L2cache = l2_cache,
@@ -130,8 +127,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
- cntrl_count += 1
-
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -183,7 +178,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
start_index_bit = pf_start_bit)
dir_cntrl = Directory_Controller(version = i,
- cntrl_id = cntrl_count,
directory = \
RubyDirectoryMemory( \
version = i,
@@ -206,8 +200,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
- cntrl_count += 1
-
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -216,7 +208,6 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
- cntrl_id = cntrl_count,
dma_sequencer = dma_seq,
transitions_per_cycle = options.ports,
ruby_system = ruby_system)
@@ -228,10 +219,7 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
if options.recycle_latency:
dma_cntrl.recycle_latency = options.recycle_latency
- cntrl_count += 1
-
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
-
topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)