1 files changed, 34 insertions, 16 deletions

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 41c507503..f35ab20c4 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -49,12 +49,13 @@ class L2Cache(RubyCache):
     latency = 15
     size = 1048576
 
-def create_system(options, physmem):
+def create_system(options, phys_mem, piobus, dma_devices):
     
     if buildEnv['PROTOCOL'] != 'MOESI_hammer':
         panic("This script requires the MOESI_hammer protocol to be built.")
 
-    sequencers = []
+    cpu_sequencers = []
+    
     #
     # The ruby network creation expects the list of nodes in the system to be
     # consistent with the NetDest list.  Therefore the l1 controller nodes must be
@@ -68,11 +69,10 @@ def create_system(options, physmem):
     # Must create the individual controllers before the network to ensure the
     # controller constructors are called before the network constructor
     #
-    for i in range(options.num_cpus):
+    
+    for i in xrange(options.num_cpus):
         #
         # First create the Ruby objects associated with this cpu
-        # Eventually this code should go in a python file specific to the
-        # MOESI_hammer protocol
         #
         l1i_profiler = CacheProfiler(description = ("l1i_%s_profiler" % i))
         l1i_cache = L1Cache(cache_profiler = l1i_profiler)
@@ -85,33 +85,51 @@ def create_system(options, physmem):
 
         cpu_seq = RubySequencer(icache = l1i_cache,
                                 dcache = l1d_cache,
-                                funcmem_port = physmem.port)
+                                physMemPort = phys_mem.port,
+                                physmem = phys_mem)
+
+        if piobus != None:
+            cpu_seq.pio_port = piobus.port
 
         l1_cntrl = L1Cache_Controller(version = i,
                                       sequencer = cpu_seq,
                                       L1IcacheMemory = l1i_cache,
                                       L1DcacheMemory = l1d_cache,
                                       L2cacheMemory = l2_cache)
+        #
+        # Add controllers and sequencers to the appropriate lists
+        #
+        cpu_sequencers.append(cpu_seq)
+        l1_cntrl_nodes.append(l1_cntrl)
+
+    for i in xrange(options.num_dirs):
+        #
+        # Create the Ruby objects associated with the directory controller
+        #
 
         mem_cntrl = RubyMemoryControl(version = i)
 
         dir_cntrl = Directory_Controller(version = i,
-                                         directory = RubyDirectoryMemory(),
+                                         directory = \
+                                           RubyDirectoryMemory(version = i),
                                          memBuffer = mem_cntrl)
 
-        dma_cntrl = DMA_Controller(version = i,
-                                   dma_sequencer = DMASequencer())
+        dir_cntrl_nodes.append(dir_cntrl)
 
+    for i, dma_device in enumerate(dma_devices):
         #
-        # Add controllers and sequencers to the appropriate lists
-        # As noted above: Independent list are track to maintain the order of
-        # nodes/controllers assumed by the ruby network
+        # Create the Ruby objects associated with the dma controller
         #
-        sequencers.append(cpu_seq)
-        l1_cntrl_nodes.append(l1_cntrl)
-        dir_cntrl_nodes.append(dir_cntrl)
+        dma_seq = DMASequencer(version = i,
+                               physMemPort = phys_mem.port,
+                               physmem = phys_mem)
+        
+        dma_cntrl = DMA_Controller(version = i,
+                                   dma_sequencer = dma_seq)
+
+        dma_cntrl.dma_sequencer.port = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
     all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
 
-    return (sequencers, dir_cntrl_nodes, all_cntrls)
+    return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)