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-rw-r--r--configs/ruby/MESI_Three_Level.py28
-rw-r--r--configs/ruby/MESI_Two_Level.py35
-rw-r--r--configs/ruby/MI_example.py25
-rw-r--r--configs/ruby/MOESI_CMP_directory.py29
-rw-r--r--configs/ruby/MOESI_CMP_token.py35
-rw-r--r--configs/ruby/MOESI_hammer.py31
-rw-r--r--configs/ruby/Network_test.py14
-rw-r--r--configs/ruby/Ruby.py56
8 files changed, 204 insertions, 49 deletions
diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py
index ee6ceccf9..1ddffc34a 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -129,7 +129,19 @@ def create_system(options, system, dma_ports, ruby_system):
cpu_sequencers.append(cpu_seq)
l0_cntrl_nodes.append(l0_cntrl)
l1_cntrl_nodes.append(l1_cntrl)
- l0_cntrl.peer = l1_cntrl
+
+ # Connect the L0 and L1 controllers
+ l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
+ l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
+
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestToL2 = ruby_system.network.slave
+ l1_cntrl.responseToL2 = ruby_system.network.slave
+ l1_cntrl.unblockToL2 = ruby_system.network.slave
+
+ l1_cntrl.requestFromL2 = ruby_system.network.master
+ l1_cntrl.responseFromL2 = ruby_system.network.master
+
for j in xrange(num_l2caches_per_cluster):
l2_cache = L2Cache(size = options.l2_size,
@@ -146,6 +158,15 @@ def create_system(options, system, dma_ports, ruby_system):
i * num_l2caches_per_cluster + j))
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.unblockToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -183,6 +204,11 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index c70c599c7..8d75fe22e 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -108,12 +108,19 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.unblockFromL1Cache = ruby_system.network.slave
+
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -132,10 +139,21 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.unblockToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system
# clk_divider value is a fix to pass regression.
@@ -169,10 +187,14 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
- #
# Create the Ruby objects associated with the dma controller
- #
dma_seq = DMASequencer(version = i,
ruby_system = ruby_system)
@@ -185,6 +207,11 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ # Connect the dma controller to the network
+ dma_cntrl.responseFromDir = ruby_system.network.master
+ dma_cntrl.requestToDir = ruby_system.network.slave
+
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 012479250..f671adbaa 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -94,12 +94,17 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.forwardToCache = ruby_system.network.master
+ l1_cntrl.responseToCache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -139,6 +144,15 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -155,8 +169,11 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ # Connect the directory controllers and the network
+ dma_cntrl.requestToDir = ruby_system.network.master
+ dma_cntrl.responseFromDir = ruby_system.network.slave
- topology = create_topology(all_cntrls, options)
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index aa474209f..d390efa0d 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -104,12 +104,17 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -128,10 +133,21 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system.
# clk_divider value is a fix to pass regression.
@@ -164,6 +180,13 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -180,11 +203,11 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 36a532574..ef793530b 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -124,12 +124,20 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
+
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+ l1_cntrl.persistentToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -149,6 +157,17 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+ l2_cntrl.persistentToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -186,6 +205,18 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.persistentToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.requestFromDir = ruby_system.network.slave
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.persistentFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index de98fd0c2..c13a6cc3a 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -119,12 +119,22 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.recycle_latency = options.recycle_latency
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
+
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controller and the network
+ # Connect the buffers from the controller to network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.unblockFromCache = ruby_system.network.slave
+
+ # Connect the buffers from the network to the controller
+ l1_cntrl.forwardToCache = ruby_system.network.master
+ l1_cntrl.responseToCache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -198,6 +208,17 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controller to the network
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+
+ dir_cntrl.unblockToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -217,7 +238,11 @@ def create_system(options, system, dma_ports, ruby_system):
if options.recycle_latency:
dma_cntrl.recycle_latency = options.recycle_latency
+ # Connect the dma controller to the network
+ dma_cntrl.responseFromDir = ruby_system.network.slave
+ dma_cntrl.requestToDir = ruby_system.network.master
+
+
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index 553927bb7..7e4379c0d 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -91,12 +91,16 @@ def create_system(options, system, dma_ports, ruby_system):
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.forwardFromCache = ruby_system.network.slave
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -114,6 +118,12 @@ def create_system(options, system, dma_ports, ruby_system):
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.forwardToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+
+
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes
topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index d9517456b..3c43fa6c6 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -106,31 +106,7 @@ def create_system(options, system, piobus = None, dma_ports = []):
system.ruby = RubySystem(no_mem_vec = options.use_map)
ruby = system.ruby
- protocol = buildEnv['PROTOCOL']
- exec "import %s" % protocol
- try:
- (cpu_sequencers, dir_cntrls, topology) = \
- eval("%s.create_system(options, system, dma_ports, ruby)"
- % protocol)
- except:
- print "Error: could not create sytem for ruby protocol %s" % protocol
- raise
-
- # Create a port proxy for connecting the system port. This is
- # independent of the protocol and kept in the protocol-agnostic
- # part (i.e. here).
- sys_port_proxy = RubyPortProxy(ruby_system = ruby)
- # Give the system port proxy a SimObject parent without creating a
- # full-fledged controller
- system.sys_port_proxy = sys_port_proxy
-
- # Connect the system port for loading of binaries etc
- system.system_port = system.sys_port_proxy.slave
-
-
- #
# Set the network classes based on the command line options
- #
if options.garnet_network == "fixed":
NetworkClass = GarnetNetwork_d
IntLinkClass = GarnetIntLink_d
@@ -152,10 +128,34 @@ def create_system(options, system, piobus = None, dma_ports = []):
RouterClass = Switch
InterfaceClass = None
+ # Instantiate the network object so that the controllers can connect to it.
+ network = NetworkClass(ruby_system = ruby, topology = options.topology,
+ routers = [], ext_links = [], int_links = [], netifs = [])
+ ruby.network = network
+
+ protocol = buildEnv['PROTOCOL']
+ exec "import %s" % protocol
+ try:
+ (cpu_sequencers, dir_cntrls, topology) = \
+ eval("%s.create_system(options, system, dma_ports, ruby)"
+ % protocol)
+ except:
+ print "Error: could not create sytem for ruby protocol %s" % protocol
+ raise
+
+ # Create a port proxy for connecting the system port. This is
+ # independent of the protocol and kept in the protocol-agnostic
+ # part (i.e. here).
+ sys_port_proxy = RubyPortProxy(ruby_system = ruby)
+
+ # Give the system port proxy a SimObject parent without creating a
+ # full-fledged controller
+ system.sys_port_proxy = sys_port_proxy
+
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.sys_port_proxy.slave
# Create the network topology
- network = NetworkClass(ruby_system = ruby, topology = topology.description,
- routers = [], ext_links = [], int_links = [], netifs = [])
topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
RouterClass)
@@ -168,14 +168,12 @@ def create_system(options, system, piobus = None, dma_ports = []):
network.enable_fault_model = True
network.fault_model = FaultModel()
- #
# Loop through the directory controlers.
# Determine the total memory size of the ruby system and verify it is equal
# to physmem. However, if Ruby memory is using sparse memory in SE
# mode, then the system should not back-up the memory state with
# the Memory Vector and thus the memory size bytes should stay at 0.
# Also set the numa bits to the appropriate values.
- #
total_mem_size = MemorySize('0B')
ruby.block_size_bytes = options.cacheline_size
@@ -196,8 +194,6 @@ def create_system(options, system, piobus = None, dma_ports = []):
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(total_mem_size.value == phys_mem_size)
-
- ruby.network = network
ruby.mem_size = total_mem_size
# Connect the cpu sequencers and the piobus