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-rw-r--r--configs/ruby/MESI_CMP_directory.py15
-rw-r--r--configs/ruby/MI_example.py11
-rw-r--r--configs/ruby/MOESI_CMP_directory.py15
-rw-r--r--configs/ruby/MOESI_CMP_token.py21
-rw-r--r--configs/ruby/MOESI_hammer.py19
-rw-r--r--configs/ruby/Network_test.py11
-rw-r--r--configs/ruby/Ruby.py2
7 files changed, 50 insertions, 44 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 4bd969be5..f0e072f90 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 5f5703d4e..5018f2c18 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -78,20 +78,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 15558a62d..c8b16fc5d 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 5b6e21f33..36999be5d 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -97,18 +97,8 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
@@ -122,6 +112,17 @@ def create_system(options, system, piobus, dma_devices):
no_mig_atomic = not \
options.allow_atomic_migration)
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 4a0391264..7e789d8e3 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -96,24 +96,25 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache,
+ no_mig_atomic = not \
+ options.allow_atomic_migration)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache,
- no_mig_atomic = not \
- options.allow_atomic_migration)
-
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index 75ec9099e..308354f0f 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -83,20 +83,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
using_network_tester = True)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 604bb7a73..3c58dfd2f 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -145,7 +145,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
tracer = RubyTracer(),
mem_size = total_mem_size)
- ruby.cpu_ruby_ports = cpu_sequencers
+ ruby._cpu_ruby_ports = cpu_sequencers
ruby.random_seed = options.random_seed
return ruby
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 01:32:45 +0000