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-rw-r--r--configs/splash2/cluster.py14
-rw-r--r--configs/splash2/run.py8
2 files changed, 11 insertions, 11 deletions
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 4a9446794..a6244a9ef 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -221,19 +221,19 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.slave
+system.l2.mem_side = system.membus.master
# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cluster in clusters:
- cluster.l1.cpu_side = cluster.clusterbus.port
- cluster.l1.mem_side = system.toL2bus.port
+ cluster.l1.cpu_side = cluster.clusterbus.master
+ cluster.l1.mem_side = system.toL2bus.slave
for cpu in cluster.cpus:
- cpu.icache_port = cluster.clusterbus.port
- cpu.dcache_port = cluster.clusterbus.port
+ cpu.icache_port = cluster.clusterbus.slave
+ cpu.dcache_port = cluster.clusterbus.slave
# ----------------------
# Define the root
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 23e986b09..2681a222d 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -207,10 +207,10 @@ system.l2 = L2(size = options.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
-system.physmem.port = system.membus.port
-system.l2.cpu_side = system.toL2bus.port
-system.l2.mem_side = system.membus.port
-system.system_port = system.membus.port
+system.physmem.port = system.membus.master
+system.l2.cpu_side = system.toL2bus.master
+system.l2.mem_side = system.membus.slave
+system.system_port = system.membus.slave
# ----------------------
# Connect the L2 cache and clusters together