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-rw-r--r--configs/common/Benchmarks.py88
-rw-r--r--configs/common/FSConfig.py2
-rw-r--r--configs/example/fs.py76
-rw-r--r--configs/example/memtest.py138
4 files changed, 227 insertions, 77 deletions
diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index bb1ac1ab5..1f272517a 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -28,7 +28,7 @@
from SysPaths import *
-class Machine:
+class SysConfig:
def __init__(self, script=None, mem=None, disk=None):
self.scriptname = script
self.diskname = disk
@@ -52,54 +52,54 @@ class Machine:
else:
return env.get('LINUX_IMAGE', disk('linux-latest.img'))
-#Benchmarks are defined as a key in a dict which is a list of Machines
+# Benchmarks are defined as a key in a dict which is a list of SysConfigs
# The first defined machine is the test system, the others are driving systems
-# Currently there is only support for 1 or 2 machines
-Benchmarks = {}
-Benchmarks['PovrayBench'] = [Machine('povray-bench.rcS', '512MB', 'povray.img')]
-Benchmarks['PovrayAutumn'] = [Machine('povray-autumn.rcS', '512MB', 'povray.img')]
-Benchmarks['NetperfStream'] = [Machine('netperf-stream-client.rcS'),
- Machine('netperf-server.rcS')]
-Benchmarks['NetperfStreamNT'] = [Machine('netperf-stream-nt-client.rcS'),
- Machine('netperf-server.rcS')]
-Benchmarks['NetperfMaerts'] = [Machine('netperf-maerts-client.rcS'),
- Machine('netperf-server.rcS')]
-Benchmarks['SurgeStandard'] = [Machine('surge-server.rcS', '512MB'),
- Machine('surge-client.rcS', '256MB')]
-Benchmarks['SurgeSpecweb'] = [Machine('spec-surge-server.rcS', '512MB'),
- Machine('spec-surge-client.rcS', '256MB')]
-Benchmarks['Nhfsstone'] = [Machine('nfs-server-nhfsstone.rcS', '512MB'),
- Machine('nfs-client-nhfsstone.rcS')]
-Benchmarks['Nfs'] = [Machine('nfs-server.rcS', '900MB'),
- Machine('nfs-client-dbench.rcS')]
-Benchmarks['NfsTcp'] = [Machine('nfs-server.rcS', '900MB'),
- Machine('nfs-client-tcp.rcS')]
-Benchmarks['IScsiInitiator'] = [Machine('iscsi-client.rcS', '512MB'),
- Machine('iscsi-server.rcS', '512MB')]
-Benchmarks['IScsiTarget'] = [Machine('iscsi-server.rcS', '512MB'),
- Machine('iscsi-client.rcS', '512MB')]
-Benchmarks['Validation'] = [Machine('iscsi-server.rcS', '512MB'),
- Machine('iscsi-client.rcS', '512MB')]
-Benchmarks['Ping'] = [Machine('ping-server.rcS',),
- Machine('ping-client.rcS')]
+Benchmarks = {
+ 'PovrayBench': [SysConfig('povray-bench.rcS', '512MB', 'povray.img')],
+ 'PovrayAutumn': [SysConfig('povray-autumn.rcS', '512MB', 'povray.img')],
+ 'NetperfStream': [SysConfig('netperf-stream-client.rcS'),
+ SysConfig('netperf-server.rcS')],
+ 'NetperfStreamNT': [SysConfig('netperf-stream-nt-client.rcS'),
+ SysConfig('netperf-server.rcS')],
+ 'NetperfMaerts': [SysConfig('netperf-maerts-client.rcS'),
+ SysConfig('netperf-server.rcS')],
+ 'SurgeStandard': [SysConfig('surge-server.rcS', '512MB'),
+ SysConfig('surge-client.rcS', '256MB')],
+ 'SurgeSpecweb': [SysConfig('spec-surge-server.rcS', '512MB'),
+ SysConfig('spec-surge-client.rcS', '256MB')],
+ 'Nhfsstone': [SysConfig('nfs-server-nhfsstone.rcS', '512MB'),
+ SysConfig('nfs-client-nhfsstone.rcS')],
+ 'Nfs': [SysConfig('nfs-server.rcS', '900MB'),
+ SysConfig('nfs-client-dbench.rcS')],
+ 'NfsTcp': [SysConfig('nfs-server.rcS', '900MB'),
+ SysConfig('nfs-client-tcp.rcS')],
+ 'IScsiInitiator': [SysConfig('iscsi-client.rcS', '512MB'),
+ SysConfig('iscsi-server.rcS', '512MB')],
+ 'IScsiTarget': [SysConfig('iscsi-server.rcS', '512MB'),
+ SysConfig('iscsi-client.rcS', '512MB')],
+ 'Validation': [SysConfig('iscsi-server.rcS', '512MB'),
+ SysConfig('iscsi-client.rcS', '512MB')],
+ 'Ping': [SysConfig('ping-server.rcS',),
+ SysConfig('ping-client.rcS')],
-Benchmarks['ValAccDelay'] = [Machine('devtime.rcS', '512MB')]
-Benchmarks['ValAccDelay2'] = [Machine('devtimewmr.rcS', '512MB')]
-Benchmarks['ValMemLat'] = [Machine('micro_memlat.rcS', '512MB')]
-Benchmarks['ValMemLat2MB'] = [Machine('micro_memlat2mb.rcS', '512MB')]
-Benchmarks['ValMemLat8MB'] = [Machine('micro_memlat8mb.rcS', '512MB')]
-Benchmarks['ValMemLat'] = [Machine('micro_memlat8.rcS', '512MB')]
-Benchmarks['ValTlbLat'] = [Machine('micro_tlblat.rcS', '512MB')]
-Benchmarks['ValSysLat'] = [Machine('micro_syscall.rcS', '512MB')]
-Benchmarks['ValCtxLat'] = [Machine('micro_ctx.rcS', '512MB')]
-Benchmarks['ValStream'] = [Machine('micro_stream.rcS', '512MB')]
-Benchmarks['ValStreamScale'] = [Machine('micro_streamscale.rcS', '512MB')]
-Benchmarks['ValStreamCopy'] = [Machine('micro_streamcopy.rcS', '512MB')]
+ 'ValAccDelay': [SysConfig('devtime.rcS', '512MB')],
+ 'ValAccDelay2': [SysConfig('devtimewmr.rcS', '512MB')],
+ 'ValMemLat': [SysConfig('micro_memlat.rcS', '512MB')],
+ 'ValMemLat2MB': [SysConfig('micro_memlat2mb.rcS', '512MB')],
+ 'ValMemLat8MB': [SysConfig('micro_memlat8mb.rcS', '512MB')],
+ 'ValMemLat': [SysConfig('micro_memlat8.rcS', '512MB')],
+ 'ValTlbLat': [SysConfig('micro_tlblat.rcS', '512MB')],
+ 'ValSysLat': [SysConfig('micro_syscall.rcS', '512MB')],
+ 'ValCtxLat': [SysConfig('micro_ctx.rcS', '512MB')],
+ 'ValStream': [SysConfig('micro_stream.rcS', '512MB')],
+ 'ValStreamScale': [SysConfig('micro_streamscale.rcS', '512MB')],
+ 'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
-
-Benchmarks['bnAn'] = [Machine('/z/saidi/work/m5.newmem.head/configs/boot/bn-app.rcS', '128MB', '/z/saidi/work/bottleneck/bnimg.img')]
+ 'bnAn': [SysConfig('/z/saidi/work/m5.newmem.head/configs/boot/bn-app.rcS',
+ '128MB', '/z/saidi/work/bottleneck/bnimg.img')]
+}
benchs = Benchmarks.keys()
benchs.sort()
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 470dc8867..05888b10b 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -49,7 +49,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self = LinuxAlphaSystem()
if not mdesc:
# generic system
- mdesc = Machine()
+ mdesc = SysConfig()
self.readfile = mdesc.script()
self.iobus = Bus(bus_id=0)
self.membus = Bus(bus_id=1)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 460fb68fb..a5b8772af 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -42,6 +42,8 @@ parser = optparse.OptionParser()
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-n", "--num_cpus", type="int", default=1)
+parser.add_option("--caches", action="store_true")
parser.add_option("-m", "--maxtick", type="int")
parser.add_option("--maxtime", type="float")
parser.add_option("--dual", action="store_true",
@@ -64,53 +66,63 @@ if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
+class MyCache(BaseCache):
+ assoc = 2
+ block_size = 64
+ latency = 1
+ mshrs = 10
+ tgts_per_mshr = 5
+ protocol = CoherenceProtocol(protocol='moesi')
+
+# client system CPU is always simple... note this is an assignment of
+# a class, not an instance.
+ClientCPUClass = AtomicSimpleCPU
+client_mem_mode = 'atomic'
+
if options.detailed:
- cpu = DerivO3CPU()
- cpu2 = DerivO3CPU()
- mem_mode = 'timing'
+ ServerCPUClass = DerivO3CPU
+ server_mem_mode = 'timing'
elif options.timing:
- cpu = TimingSimpleCPU()
- cpu2 = TimingSimpleCPU()
- mem_mode = 'timing'
+ ServerCPUClass = TimingSimpleCPU
+ server_mem_mode = 'timing'
else:
- cpu = AtomicSimpleCPU()
- cpu2 = AtomicSimpleCPU()
- mem_mode = 'atomic'
+ ServerCPUClass = AtomicSimpleCPU
+ server_mem_mode = 'atomic'
-cpu.clock = '2GHz'
-cpu2.clock = '2GHz'
-cpu.cpu_id = 0
-cpu2.cpu_id = 0
+ServerCPUClass.clock = '2GHz'
+ClientCPUClass.clock = '2GHz'
if options.benchmark:
- if options.benchmark not in Benchmarks:
+ try:
+ bm = Benchmarks[options.benchmark]
+ except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
-
- bm = Benchmarks[options.benchmark]
else:
if options.dual:
- bm = [Machine(), Machine()]
+ bm = [SysConfig(), SysConfig()]
else:
- bm = [Machine()]
+ bm = [SysConfig()]
+
+server_sys = makeLinuxAlphaSystem(server_mem_mode, bm[0])
+np = options.num_cpus
+server_sys.cpu = [ServerCPUClass(cpu_id=i) for i in xrange(np)]
+for i in xrange(np):
+ if options.caches:
+ server_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'),
+ MyCache(size = '64kB'))
+ server_sys.cpu[i].connectMemPorts(server_sys.membus)
+ server_sys.cpu[i].mem = server_sys.physmem
if len(bm) == 2:
- s1 = makeLinuxAlphaSystem(mem_mode, bm[0])
- s1.cpu = cpu
- cpu.connectMemPorts(s1.membus)
- cpu.mem = s1.physmem
- s2 = makeLinuxAlphaSystem(mem_mode, bm[1])
- s2.cpu = cpu2
- cpu2.connectMemPorts(s2.membus)
- cpu2.mem = s2.physmem
- root = makeDualRoot(s1, s2, options.etherdump)
+ client_sys = makeLinuxAlphaSystem(client_mem_mode, bm[1])
+ client_sys.cpu = ClientCPUClass(cpu_id=0)
+ client_sys.cpu.connectMemPorts(client_sys.membus)
+ client_sys.cpu.mem = client_sys.physmem
+ root = makeDualRoot(server_sys, client_sys, options.etherdump)
elif len(bm) == 1:
- root = Root(clock = '1THz',
- system = makeLinuxAlphaSystem(mem_mode, bm[0]))
- root.system.cpu = cpu
- cpu.connectMemPorts(root.system.membus)
- cpu.mem = root.system.physmem
+ root = Root(clock = '1THz', system = server_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
new file mode 100644
index 000000000..141ecfd8e
--- /dev/null
+++ b/configs/example/memtest.py
@@ -0,0 +1,138 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+import os, optparse, sys
+m5.AddToPath('../common')
+
+parser = optparse.OptionParser()
+
+parser.add_option("--caches", action="store_true")
+parser.add_option("-t", "--timing", action="store_true")
+parser.add_option("-m", "--maxtick", type="int")
+parser.add_option("-l", "--maxloads", default = "1000000000000", type="int")
+parser.add_option("-n", "--numtesters", default = "8", type="int")
+parser.add_option("-p", "--protocol",
+ default="moesi",
+ help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)")
+
+(options, args) = parser.parse_args()
+
+if args:
+ print "Error: script doesn't take any positional arguments"
+ sys.exit(1)
+
+# --------------------
+# Base L1 Cache
+# ====================
+
+class L1(BaseCache):
+ latency = 1
+ block_size = 64
+ mshrs = 12
+ tgts_per_mshr = 8
+ protocol = CoherenceProtocol(protocol=options.protocol)
+
+# ----------------------
+# Base L2 Cache
+# ----------------------
+
+class L2(BaseCache):
+ block_size = 64
+ latency = 10
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+#MAX CORES IS 8 with the false sharing method
+if options.numtesters > 8:
+ print "Error: NUmber of testers limited to 8 because of false sharing"
+ sys,exit(1)
+
+if options.timing:
+ cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50,
+ percent_uncacheable=10, progress_interval=1000)
+ for i in xrange(options.numtesters) ]
+else:
+ cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50,
+ percent_uncacheable=10, progress_interval=1000)
+ for i in xrange(options.numtesters) ]
+# system simulated
+system = System(cpu = cpus, funcmem = PhysicalMemory(),
+ physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16))
+
+# l2cache & bus
+if options.caches:
+ system.toL2Bus = Bus(clock="500GHz", width=16)
+ system.l2c = L2(size='64kB', assoc=8)
+ system.l2c.cpu_side = system.toL2Bus.port
+
+ # connect l2c to membus
+ system.l2c.mem_side = system.membus.port
+
+which_port = 0
+# add L1 caches
+for cpu in cpus:
+ if options.caches:
+ cpu.l1c = L1(size = '32kB', assoc = 4)
+ cpu.test = cpu.l1c.cpu_side
+ cpu.l1c.mem_side = system.toL2Bus.port
+ else:
+ cpu.test = system.membus.port
+ if which_port == 0:
+ system.funcmem.port = cpu.functional
+ which_port = 1
+ else:
+ system.funcmem.functional = cpu.functional
+
+
+# connect memory to membus
+system.physmem.port = system.membus.port
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( system = system )
+if options.timing:
+ root.system.mem_mode = 'timing'
+else:
+ root.system.mem_mode = 'atomic'
+
+# instantiate configuration
+m5.instantiate(root)
+
+# simulate until program terminates
+if options.maxtick:
+ exit_event = m5.simulate(options.maxtick)
+else:
+ exit_event = m5.simulate()
+
+print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()