summaryrefslogtreecommitdiff
path: root/configs
diff options
context:
space:
mode:
Diffstat (limited to 'configs')
-rw-r--r--configs/common/CacheConfig.py2
-rw-r--r--configs/common/FSConfig.py26
-rw-r--r--configs/example/memtest.py2
-rw-r--r--configs/example/se.py2
-rw-r--r--configs/splash2/cluster.py11
-rw-r--r--configs/splash2/run.py4
6 files changed, 24 insertions, 23 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 009cb1bf6..bc724f65f 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -43,7 +43,7 @@ def config_cache(options, system):
system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
block_size=options.cacheline_size)
- system.tol2bus = Bus()
+ system.tol2bus = CoherentBus()
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 8e4be3137..c9e28a5f6 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -50,7 +50,7 @@ class CowIdeDisk(IdeDisk):
def childImage(self, ci):
self.image.child.image_file = ci
-class MemBus(Bus):
+class MemBus(CoherentBus):
badaddr_responder = BadAddr()
default = Self.badaddr_responder.pio
@@ -67,8 +67,8 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
+ self.iobus = NoncoherentBus()
+ self.membus = MemBus()
# By default the bridge responds to all addresses above the I/O
# base address (including the PCI config space)
self.bridge = Bridge(delay='50ns', nack_delay='4ns',
@@ -117,7 +117,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
self.readfile = mdesc.script()
# Create pio bus to connect all device pio ports to rubymem's pio port
- self.piobus = Bus(bus_id=0)
+ self.piobus = NoncoherentBus()
#
# Pio functional accesses from devices need direct access to memory
@@ -172,8 +172,8 @@ def makeSparcSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
+ self.iobus = NoncoherentBus()
+ self.membus = MemBus()
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
@@ -237,8 +237,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
+ self.iobus = NoncoherentBus()
+ self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.bridge.master = self.iobus.slave
@@ -320,8 +320,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = Bus(bus_id=0)
- self.membus = MemBus(bus_id=1)
+ self.iobus = NoncoherentBus()
+ self.membus = MemBus()
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = SimpleMemory(range = AddrRange('1GB'))
self.bridge.master = self.iobus.slave
@@ -363,11 +363,11 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
interrupts_address_space_base = 0xa000000000000000
APIC_range_size = 1 << 12;
- x86_sys.membus = MemBus(bus_id=1)
+ x86_sys.membus = MemBus()
x86_sys.physmem.port = x86_sys.membus.master
# North Bridge
- x86_sys.iobus = Bus(bus_id=0)
+ x86_sys.iobus = NoncoherentBus()
x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
@@ -402,7 +402,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.piobus = Bus(bus_id=0)
+ x86_sys.piobus = NoncoherentBus()
#
# Pio functional accesses from devices need direct access to memory
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 2dcccbba6..590378920 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -148,7 +148,7 @@ def make_level(spec, prototypes, attach_obj, attach_port):
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = Bus(clock="500MHz", width=16)
+ new_bus = CoherentBus(clock="500MHz", width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff --git a/configs/example/se.py b/configs/example/se.py
index 8324bea4e..83abbd2f3 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -153,7 +153,7 @@ np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = SimpleMemory(range=AddrRange("512MB")),
- membus = Bus(), mem_mode = test_mem_mode)
+ membus = CoherentBus(), mem_mode = test_mem_mode)
# Sanity check
if options.fastmem and (options.caches or options.l2cache):
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index dd8ab784a..d7e32a414 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -173,7 +173,7 @@ if options.timing:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = Bus(clock=busFrequency)
+ cluster.clusterbus = CoherentBus(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -186,7 +186,7 @@ elif options.detailed:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = Bus(clock=busFrequency)
+ cluster.clusterbus = CoherentBus(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -199,7 +199,7 @@ else:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = Bus(clock=busFrequency)
+ cluster.clusterbus = CoherentBus(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -212,9 +212,10 @@ else:
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
- physmem = SimpleMemory(), membus = Bus(clock = busFrequency))
+ physmem = SimpleMemory(),
+ membus = CoherentBus(clock = busFrequency))
-system.toL2bus = Bus(clock = busFrequency)
+system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 40dafceff..48e255c52 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -198,9 +198,9 @@ else:
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
- membus = Bus(clock = busFrequency))
+ membus = CoherentBus(clock = busFrequency))
-system.toL2bus = Bus(clock = busFrequency)
+system.toL2bus = CoherentBus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 03:21:37 +0000