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-rw-r--r--configs/common/FSConfig.py58
-rw-r--r--configs/example/fs.py31
2 files changed, 86 insertions, 3 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 834e9bd0a..d46bec410 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
@@ -170,6 +182,52 @@ def makeSparcSystem(mem_mode, mdesc = None):
return self
+def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
+ machine_type = None):
+ if bare_metal:
+ self = ArmSystem()
+ else:
+ self = LinuxArmSystem()
+
+ if not mdesc:
+ # generic system
+ mdesc = SysConfig()
+
+ self.readfile = mdesc.script()
+ self.iobus = Bus(bus_id=0)
+ self.membus = MemBus(bus_id=1)
+ self.membus.badaddr_responder.warn_access = "warn"
+ self.bridge = Bridge(delay='50ns', nack_delay='4ns')
+ self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
+ self.bridge.side_a = self.iobus.port
+ self.bridge.side_b = self.membus.port
+ self.physmem.port = self.membus.port
+
+ self.mem_mode = mem_mode
+
+ if machine_type == "RealView_PBX":
+ self.realview = RealViewPBX()
+ elif machine_type == "RealView_EB":
+ self.realview = RealViewEB()
+ else:
+ print "Unknown Machine Type"
+ sys.exit(1)
+
+ if not bare_metal and machine_type:
+ self.machine_type = machine_type
+ elif bare_metal:
+ self.realview.uart.end_on_eot = True
+
+ self.realview.attachOnChipIO(self.membus)
+ self.realview.attachIO(self.iobus)
+
+ self.intrctrl = IntrControl()
+ self.terminal = Terminal()
+ self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps'
+
+ return self
+
+
def makeLinuxMipsSystem(mem_mode, mdesc = None):
class BaseMalta(Malta):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index a5a5661f0..a45b48c76 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -56,7 +68,11 @@ parser = optparse.OptionParser()
# System options
parser.add_option("--kernel", action="store", type="string")
parser.add_option("--script", action="store", type="string")
-
+if buildEnv['TARGET_ISA'] == "arm":
+ parser.add_option("--bare-metal", action="store_true",
+ help="Provide the raw system without the linux specific bits")
+ parser.add_option("--machine-type", action="store", type="choice",
+ choices=ArmMachineType.map.keys(), default="RealView_PBX")
# Benchmark options
parser.add_option("--dual", action="store_true",
help="Simulate two systems attached with an ethernet link")
@@ -112,6 +128,9 @@ elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, np, bm[0])
+elif buildEnv['TARGET_ISA'] == "arm":
+ test_sys = makeLinuxArmSystem(test_mem_mode, bm[0],
+ bare_metal=options.bare_metal, machine_type=options.machine_type)
else:
fatal("incapable of building non-alpha or non-sparc full system!")
@@ -126,9 +145,13 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
CacheConfig.config_cache(options, test_sys)
if options.caches or options.l2cache:
+ if bm[0]:
+ mem_size = bm[0].mem()
+ else:
+ mem_size = SysConfig().mem()
test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
- test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
- test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
+ test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
+ test_sys.iocache = IOCache(addr_range=mem_size)
test_sys.iocache.cpu_side = test_sys.iobus.port
test_sys.iocache.mem_side = test_sys.membus.port
@@ -148,6 +171,8 @@ if len(bm) == 2:
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeX86System(drive_mem_mode, np, bm[1])
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
drive_sys.cpu = DriveCPUClass(cpu_id=0)
drive_sys.cpu.connectMemPorts(drive_sys.membus)
if options.fastmem: