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-rw-r--r--configs/common/MemConfig.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 7f737761e..0b5011c36 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -66,10 +66,6 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
# Only do this for DRAMs
if issubclass(cls, m5.objects.DRAMCtrl):
- # Inform each controller how many channels to account
- # for
- ctrl.channels = nbr_mem_ctrls
-
# If the channel bits are appearing after the column
# bits, we need to add the appropriate number of bits
# for the row buffer size