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-rw-r--r--configs/common/CacheConfig.py9
-rw-r--r--configs/common/Options.py1
2 files changed, 7 insertions, 3 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 233f504bc..00517dfc4 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -35,7 +35,8 @@ from Caches import *
def config_cache(options, system):
if options.l2cache:
- system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc)
+ system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
+ block_size=options.cacheline_size)
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
@@ -43,8 +44,10 @@ def config_cache(options, system):
for i in xrange(options.num_cpus):
if options.caches:
- icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc)
- dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc)
+ icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
+ block_size=options.cacheline_size)
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
diff --git a/configs/common/Options.py b/configs/common/Options.py
index e3f970676..dea7ab7df 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -46,6 +46,7 @@ parser.add_option("--l1d_assoc", type="int", default=2)
parser.add_option("--l1i_assoc", type="int", default=2)
parser.add_option("--l2_assoc", type="int", default=8)
parser.add_option("--l3_assoc", type="int", default=16)
+parser.add_option("--cacheline_size", type="int", default=64)
# Run duration options
parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,