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-rw-r--r--configs/common/CacheConfig.py4
-rw-r--r--configs/common/Simulation.py2
-rw-r--r--configs/example/ruby_mem_test.py2
3 files changed, 4 insertions, 4 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index b96a7011c..1a2c87828 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -1,6 +1,6 @@
# Copyright (c) 2012-2013, 2015 ARM Limited
# All rights reserved
-#
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
@@ -9,7 +9,7 @@
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
-#
+#
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 13edf601b..b18d65cbc 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -1,6 +1,6 @@
# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
-#
+#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index e2887410f..b6e153be4 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -142,7 +142,7 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
-
+
assert(len(cpus) == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(cpus):