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-rw-r--r--configs/common/CacheConfig.py4
-rw-r--r--configs/common/FSConfig.py98
-rw-r--r--configs/example/fs.py8
-rw-r--r--configs/example/ruby_fs.py5
-rw-r--r--configs/example/se.py4
-rw-r--r--configs/ruby/Ruby.py2
6 files changed, 61 insertions, 60 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 364b20f28..720eb9f56 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -44,8 +44,8 @@ def config_cache(options, system):
block_size=options.cacheline_size)
system.tol2bus = Bus()
- system.l2.cpu_side = system.tol2bus.port
- system.l2.mem_side = system.membus.port
+ system.l2.cpu_side = system.tol2bus.master
+ system.l2.mem_side = system.membus.slave
system.l2.num_cpus = options.num_cpus
for i in xrange(options.num_cpus):
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index c14eb38f0..8e694b8c1 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -74,21 +74,21 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.bridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
- self.tsunami.ide.pio = self.iobus.port
- self.tsunami.ide.config = self.iobus.port
- self.tsunami.ide.dma = self.iobus.port
- self.tsunami.ethernet.pio = self.iobus.port
- self.tsunami.ethernet.config = self.iobus.port
- self.tsunami.ethernet.dma = self.iobus.port
+ self.tsunami.ide.pio = self.iobus.master
+ self.tsunami.ide.config = self.iobus.master
+ self.tsunami.ide.dma = self.iobus.slave
+ self.tsunami.ethernet.pio = self.iobus.master
+ self.tsunami.ethernet.config = self.iobus.master
+ self.tsunami.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -99,7 +99,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.console = binary('console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
@@ -124,7 +124,7 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
# RubyPort currently does support functional accesses. Therefore provide
# the piobus a direct connection to physical memory
#
- self.piobus.port = physmem.port
+ self.piobus.master_port = physmem.port
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
@@ -132,12 +132,12 @@ def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
self.disk2.childImage(disk('linux-bigswap2.img'))
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.piobus)
- self.tsunami.ide.pio = self.piobus.port
- self.tsunami.ide.config = self.piobus.port
- self.tsunami.ide.dma = self.piobus.port
- self.tsunami.ethernet.pio = self.piobus.port
- self.tsunami.ethernet.config = self.piobus.port
- self.tsunami.ethernet.dma = self.piobus.port
+ self.tsunami.ide.pio = self.piobus.master
+ self.tsunami.ide.config = self.piobus.master
+ self.tsunami.ide.dma = self.piobus.slave
+ self.tsunami.ethernet.pio = self.piobus.master
+ self.tsunami.ethernet.config = self.piobus.master
+ self.tsunami.ethernet.dma = self.piobus.slave
#
# Store the dma devices for later connection to dma ruby ports.
@@ -182,18 +182,18 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.t1000.attachIO(self.iobus)
self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
- self.physmem2.port = self.membus.port
- self.rom.port = self.membus.port
- self.nvram.port = self.membus.port
- self.hypervisor_desc.port = self.membus.port
- self.partition_desc.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
+ self.physmem2.port = self.membus.master
+ self.rom.port = self.membus.master
+ self.nvram.port = self.membus.master
+ self.hypervisor_desc.port = self.membus.master
+ self.partition_desc.port = self.membus.master
self.intrctrl = IntrControl()
self.disk0 = CowMmDisk()
self.disk0.childImage(disk('disk.s10hw2'))
- self.disk0.pio = self.iobus.port
+ self.disk0.pio = self.iobus.master
# The puart0 and hvuart are placed on the IO bus, so create ranges
# for them. The remaining IO range is rather fragmented, so poke
@@ -220,7 +220,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.hypervisor_desc_bin = binary('1up-hv.bin')
self.partition_desc_bin = binary('1up-md.bin')
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
@@ -241,8 +241,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.membus = MemBus(bus_id=1)
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
self.mem_mode = mem_mode
@@ -285,7 +285,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
zero = True)
self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
size = '64MB'), zero = True)
- self.nvmem.port = self.membus.port
+ self.nvmem.port = self.membus.master
self.boot_loader = binary('boot.arm')
self.boot_loader_mem = self.nvmem
self.gic_cpu_addr = self.realview.gic.cpu_addr
@@ -295,14 +295,14 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
boot_flags += " init=/init "
self.boot_osflags = boot_flags
- self.physmem.port = self.membus.port
+ self.physmem.port = self.membus.master
self.realview.attachOnChipIO(self.membus, self.bridge)
self.realview.attachIO(self.iobus)
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
@@ -322,21 +322,21 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
self.physmem = PhysicalMemory(range = AddrRange('1GB'))
- self.bridge.master = self.iobus.port
- self.bridge.slave = self.membus.port
- self.physmem.port = self.membus.port
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+ self.physmem.port = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
- self.malta.ide.pio = self.iobus.port
- self.malta.ide.config = self.iobus.port
- self.malta.ide.dma = self.iobus.port
- self.malta.ethernet.pio = self.iobus.port
- self.malta.ethernet.config = self.iobus.port
- self.malta.ethernet.dma = self.iobus.port
+ self.malta.ide.pio = self.iobus.master
+ self.malta.ide.config = self.iobus.master
+ self.malta.ide.dma = self.iobus.slave
+ self.malta.ethernet.pio = self.iobus.master
+ self.malta.ethernet.config = self.iobus.master
+ self.malta.ethernet.dma = self.iobus.slave
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -346,7 +346,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.console = binary('mips/console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
- self.system_port = self.membus.port
+ self.system_port = self.membus.slave
return self
@@ -362,13 +362,13 @@ def connectX86ClassicSystem(x86_sys):
APIC_range_size = 1 << 12;
x86_sys.membus = MemBus(bus_id=1)
- x86_sys.physmem.port = x86_sys.membus.port
+ x86_sys.physmem.port = x86_sys.membus.master
# North Bridge
x86_sys.iobus = Bus(bus_id=0)
x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
- x86_sys.bridge.master = x86_sys.iobus.port
- x86_sys.bridge.slave = x86_sys.membus.port
+ x86_sys.bridge.master = x86_sys.iobus.slave
+ x86_sys.bridge.slave = x86_sys.membus.master
# Allow the bridge to pass through the IO APIC (two pages),
# everything in the IO address range up to the local APIC, and
# then the entire PCI address space and beyond
@@ -386,8 +386,8 @@ def connectX86ClassicSystem(x86_sys):
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns')
- x86_sys.apicbridge.slave = x86_sys.iobus.port
- x86_sys.apicbridge.master = x86_sys.membus.port
+ x86_sys.apicbridge.slave = x86_sys.iobus.master
+ x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
APIC_range_size - 1)]
@@ -395,7 +395,7 @@ def connectX86ClassicSystem(x86_sys):
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
- x86_sys.system_port = x86_sys.membus.port
+ x86_sys.system_port = x86_sys.membus.slave
def connectX86RubySystem(x86_sys):
# North Bridge
@@ -406,7 +406,7 @@ def connectX86RubySystem(x86_sys):
# RubyPort currently does support functional accesses. Therefore provide
# the piobus a direct connection to physical memory
#
- x86_sys.piobus.port = x86_sys.physmem.port
+ x86_sys.piobus.master = x86_sys.physmem.port
x86_sys.pc.attachIO(x86_sys.piobus)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index cf3dfdb89..754a0b79b 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -160,13 +160,13 @@ else:
mem_size = SysConfig().mem()
if options.caches or options.l2cache:
test_sys.iocache = IOCache(addr_range=mem_size)
- test_sys.iocache.cpu_side = test_sys.iobus.port
- test_sys.iocache.mem_side = test_sys.membus.port
+ test_sys.iocache.cpu_side = test_sys.iobus.master
+ test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(mem_size)])
- test_sys.iobridge.slave = test_sys.iobus.port
- test_sys.iobridge.master = test_sys.membus.port
+ test_sys.iobridge.slave = test_sys.iobus.master
+ test_sys.iobridge.master = test_sys.membus.slave
for i in xrange(np):
if options.fastmem:
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index d7fc45bde..04b99034c 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -130,8 +130,9 @@ for (i, cpu) in enumerate(system.cpu):
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
- cpu.interrupts.pio = system.piobus.port
- cpu.interrupts.int_port = system.piobus.port
+ cpu.interrupts.pio = system.piobus.master
+ cpu.interrupts.int_master = system.piobus.slave
+ cpu.interrupts.int_slave = system.piobus.master
root = Root(full_system = True, system = system)
diff --git a/configs/example/se.py b/configs/example/se.py
index 35025a8ff..d7b876d46 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -182,8 +182,8 @@ if options.ruby:
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
- system.system_port = system.membus.port
- system.physmem.port = system.membus.port
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
CacheConfig.config_cache(options, system)
for i in xrange(np):
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 920eac019..1c9b65894 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -106,7 +106,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
system.sys_port_proxy = sys_port_proxy
# Connect the system port for loading of binaries etc
- system.system_port = system.sys_port_proxy.port
+ system.system_port = system.sys_port_proxy.slave
#
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 00:20:38 +0000