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-rw-r--r--configs/common/FSConfig.py3
-rw-r--r--configs/common/O3_ARM_v7a.py2
-rw-r--r--configs/common/Options.py11
-rw-r--r--configs/common/cpu2000.py2
-rw-r--r--configs/example/fs.py6
-rw-r--r--configs/example/se.py9
6 files changed, 28 insertions, 5 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 8905ba2fa..58ad1a7c9 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -242,7 +242,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None,
self.realview = VExpress_ELT()
elif machine_type == "VExpress_EMM":
self.realview = VExpress_EMM()
- self.load_addr_mask = 0xffffffff
+ elif machine_type == "VExpress_EMM64":
+ self.realview = VExpress_EMM64()
else:
print "Unknown Machine Type"
sys.exit(1)
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index aedafaf4d..3b7df9988 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -139,7 +139,7 @@ class O3_ARM_v7a_3(DerivO3CPU):
backComSize = 5
forwardComSize = 5
numPhysIntRegs = 128
- numPhysFloatRegs = 128
+ numPhysFloatRegs = 192
numIQEntries = 32
numROBEntries = 40
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 2cca4ef57..209d24357 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -94,6 +94,9 @@ def addCommonOptions(parser):
default="512MB",
help="Specify the physical memory size (single memory)")
+ parser.add_option("-l", "--lpae", action="store_true")
+ parser.add_option("-V", "--virtualisation", action="store_true")
+
# Cache Options
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
@@ -197,6 +200,14 @@ def addCommonOptions(parser):
parser.add_option("--at-instruction", action="store_true", default=False,
help="""Treat value of --checkpoint-restore or --take-checkpoint as a
number of instructions.""")
+ parser.add_option("--spec-input", default="ref", type="choice",
+ choices=["ref", "test", "train", "smred", "mdred",
+ "lgred"],
+ help="Input set size for SPEC CPU2000 benchmarks.")
+ parser.add_option("--arm-iset", default="arm", type="choice",
+ choices=["arm", "thumb", "aarch64"],
+ help="ARM instruction set.")
+
def addSEOptions(parser):
# Benchmark options
diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py
index 443399234..5f01d28bf 100644
--- a/configs/common/cpu2000.py
+++ b/configs/common/cpu2000.py
@@ -663,7 +663,7 @@ class vortex(Benchmark):
stdin = None
def __init__(self, isa, os, input_set):
- if (isa == 'alpha' or isa == 'arm'):
+ if (isa in ('alpha', 'arm', 'thumb', 'aarch64')):
self.endian = 'lendian'
elif (isa == 'sparc' or isa == 'sparc32'):
self.endian = 'bendian'
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4cfb3e8e2..cb9b264d2 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -140,6 +140,12 @@ if options.kernel is not None:
if options.script is not None:
test_sys.readfile = options.script
+if options.lpae:
+ test_sys.have_lpae = True
+
+if options.virtualisation:
+ test_sys.have_virtualization = True
+
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
diff --git a/configs/example/se.py b/configs/example/se.py
index f7e7f1a65..d4f3e2dd9 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -135,9 +135,14 @@ if options.bench:
for app in apps:
try:
if buildEnv['TARGET_ISA'] == 'alpha':
- exec("workload = %s('alpha', 'tru64', 'ref')" % app)
+ exec("workload = %s('alpha', 'tru64', '%s')" % (
+ app, options.spec_input))
+ elif buildEnv['TARGET_ISA'] == 'arm':
+ exec("workload = %s('arm_%s', 'linux', '%s')" % (
+ app, options.arm_iset, options.spec_input))
else:
- exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
+ exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
+ app, options.spec_input))
multiprocesses.append(workload.makeLiveProcess())
except:
print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)