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-rw-r--r--configs/common/CacheConfig.py4
-rw-r--r--configs/common/FSConfig.py14
-rw-r--r--configs/dram/sweep.py4
-rw-r--r--configs/example/memtest.py4
-rw-r--r--configs/example/ruby_mem_test.py2
-rw-r--r--configs/example/se.py2
-rw-r--r--configs/splash2/cluster.py10
-rw-r--r--configs/splash2/run.py4
8 files changed, 22 insertions, 22 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index b467b1656..c7a724b34 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -71,8 +71,8 @@ def config_cache(options, system):
size=options.l2_size,
assoc=options.l2_assoc)
- system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
- width = 32)
+ system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain,
+ width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index cc921229e..e93bd68f2 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -50,7 +50,7 @@ class CowIdeDisk(IdeDisk):
def childImage(self, ci):
self.image.child.image_file = ci
-class MemBus(CoherentBus):
+class MemBus(CoherentXBar):
badaddr_responder = BadAddr()
default = Self.badaddr_responder.pio
@@ -71,7 +71,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
self.tsunami = BaseTsunami()
# Create the io bus to connect all device ports
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.master
@@ -134,7 +134,7 @@ def makeSparcSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.t1000 = T1000()
@@ -196,7 +196,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None,
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
self.bridge = Bridge(delay='50ns')
@@ -299,7 +299,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
- self.iobus = NoncoherentBus()
+ self.iobus = NoncoherentXBar()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.mem_ranges = [AddrRange('1GB')]
@@ -344,7 +344,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
x86_sys.membus = MemBus()
# North Bridge
- x86_sys.iobus = NoncoherentBus()
+ x86_sys.iobus = NoncoherentXBar()
x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
@@ -379,7 +379,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.iobus = NoncoherentBus()
+ x86_sys.iobus = NoncoherentXBar()
# add the ide to the list of dma devices that later need to attach to
# dma controllers
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 631d82e07..18a58b2da 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -82,9 +82,9 @@ if args:
# and address mapping
# start with the system itself, using a multi-layer 1.5 GHz
-# bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle)
+# crossbar, delivering 64 bytes / 5 cycles (one header cycle)
# which amounts to 19.2 GByte/s per layer and thus per port
-system = System(membus = NoncoherentBus(width = 16))
+system = System(membus = NoncoherentXBar(width = 16))
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
voltage_domain =
VoltageDomain(voltage = '1V'))
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index feeffa764..eaf3a52bd 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -147,7 +147,7 @@ for scale in treespec[:-2]:
# system simulated
system = System(funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentBus(),
+ funcbus = NoncoherentXBar(),
physmem = SimpleMemory(latency = "100ns"),
cache_line_size = block_size)
@@ -162,7 +162,7 @@ def make_level(spec, prototypes, attach_obj, attach_port):
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = CoherentBus(width=16)
+ new_bus = CoherentXBar(width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 99f6f4a09..4e2cde791 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -106,7 +106,7 @@ cpus = [ MemTest(atomic = False,
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentBus(),
+ funcbus = NoncoherentXBar(),
physmem = SimpleMemory(),
clk_domain = SrcClockDomain(clock = options.sys_clock),
mem_ranges = [AddrRange(options.mem_size)])
diff --git a/configs/example/se.py b/configs/example/se.py
index 8ec90599b..f5aef5c2f 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -255,7 +255,7 @@ if options.ruby:
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
- system.membus = CoherentBus()
+ system.membus = CoherentXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 1ae9a6dd5..b17c8877e 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -171,7 +171,7 @@ if options.timing:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -184,7 +184,7 @@ elif options.detailed:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -197,7 +197,7 @@ else:
for j in xrange(options.numclusters):
clusters[j].id = j
for cluster in clusters:
- cluster.clusterbus = CoherentBus(clock=busFrequency)
+ cluster.clusterbus = CoherentXBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
@@ -211,10 +211,10 @@ else:
# ----------------------
system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
physmem = SimpleMemory(),
- membus = CoherentBus(clock = busFrequency))
+ membus = CoherentXBar(clock = busFrequency))
system.clock = '1GHz'
-system.toL2bus = CoherentBus(clock = busFrequency)
+system.toL2bus = CoherentXBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 10c9a7f61..d542a9437 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -196,10 +196,10 @@ else:
# Create a system, and add system wide objects
# ----------------------
system = System(cpu = cpus, physmem = SimpleMemory(),
- membus = CoherentBus(clock = busFrequency))
+ membus = CoherentXBar(clock = busFrequency))
system.clock = '1GHz'
-system.toL2bus = CoherentBus(clock = busFrequency)
+system.toL2bus = CoherentXBar(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
# ----------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 02:32:33 +0000