diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/ruby/MESI_CMP_directory.py | 4 | ||||
| -rw-r--r-- | configs/ruby/MI_example.py | 4 | ||||
| -rw-r--r-- | configs/ruby/MOESI_CMP_directory.py | 4 | ||||
| -rw-r--r-- | configs/ruby/MOESI_CMP_token.py | 4 | ||||
| -rw-r--r-- | configs/ruby/MOESI_hammer.py | 4 | ||||
| -rw-r--r-- | configs/ruby/Network_test.py | 2 | ||||
| -rw-r--r-- | configs/ruby/Ruby.py | 5 |
7 files changed, 1 insertions, 26 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py index 4fdba3c27..28aba4a1b 100644 --- a/configs/ruby/MESI_CMP_directory.py +++ b/configs/ruby/MESI_CMP_directory.py @@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq @@ -169,8 +167,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 851001b6f..29ed23b67 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(version = i, icache = cache, dcache = cache, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq @@ -142,8 +140,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index ac582e4e6..753a3a37a 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -96,8 +96,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq @@ -166,8 +164,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py index 20b50e3af..064d6dd14 100644 --- a/configs/ruby/MOESI_CMP_token.py +++ b/configs/ruby/MOESI_CMP_token.py @@ -118,8 +118,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq @@ -190,8 +188,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index 3f89a1a90..dc9aa3392 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -111,8 +111,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(version = i, icache = l1i_cache, dcache = l1d_cache, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) l1_cntrl.sequencer = cpu_seq @@ -202,8 +200,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - physMemPort = system.physmem.port, - physmem = system.physmem, ruby_system = ruby_system) dma_cntrl = DMA_Controller(version = i, diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py index 768b14677..5c1936b51 100644 --- a/configs/ruby/Network_test.py +++ b/configs/ruby/Network_test.py @@ -88,8 +88,6 @@ def create_system(options, system, piobus, dma_devices, ruby_system): cpu_seq = RubySequencer(icache = cache, dcache = cache, - physMemPort = system.physmem.port, - physmem = system.physmem, using_network_tester = True, ruby_system = ruby_system) diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 1c9b65894..c9788b0a0 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -97,10 +97,7 @@ def create_system(options, system, piobus = None, dma_devices = []): # Create a port proxy for connecting the system port. This is # independent of the protocol and kept in the protocol-agnostic # part (i.e. here). - sys_port_proxy = RubyPortProxy(version = 0, - physMemPort = system.physmem.port, - physmem = system.physmem, - ruby_system = ruby) + sys_port_proxy = RubyPortProxy(ruby_system = ruby) # Give the system port proxy a SimObject parent without creating a # full-fledged controller system.sys_port_proxy = sys_port_proxy |