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-rw-r--r--configs/example/ruby_direct_test.py4
-rw-r--r--configs/example/ruby_fs.py8
-rw-r--r--configs/example/ruby_mem_test.py6
-rw-r--r--configs/example/ruby_network_test.py2
-rw-r--r--configs/example/ruby_random_test.py4
-rw-r--r--configs/example/se.py6
-rw-r--r--configs/ruby/MESI_CMP_directory.py15
-rw-r--r--configs/ruby/MI_example.py11
-rw-r--r--configs/ruby/MOESI_CMP_directory.py15
-rw-r--r--configs/ruby/MOESI_CMP_token.py21
-rw-r--r--configs/ruby/MOESI_hammer.py19
-rw-r--r--configs/ruby/Network_test.py11
-rw-r--r--configs/ruby/Ruby.py2
13 files changed, 65 insertions, 59 deletions
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index e744c35bd..12585b8d5 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -99,9 +99,9 @@ system.tester = RubyDirectedTester(requests_to_complete = \
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 2081a10c4..8c03e14cb 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -128,11 +128,11 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
- cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port
- cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port
+ cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index f58ebc1de..154164919 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -126,20 +126,20 @@ system.ruby = Ruby.create_system(options, \
#
system.ruby.randomization = True
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby.cpu_ruby_ports[i].port
+ cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
- system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000
+ system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
for (i, dma) in enumerate(dmas):
#
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index c2c574493..fb2a642b8 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -108,7 +108,7 @@ system = System(cpu = cpus,
system.ruby = Ruby.create_system(options, system)
i = 0
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 8c415641b..b60afc192 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -101,7 +101,7 @@ system = System(tester = tester, physmem = PhysicalMemory())
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
@@ -109,7 +109,7 @@ assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
#
system.ruby.randomization = True
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff --git a/configs/example/se.py b/configs/example/se.py
index 98fbbfbaa..9c35f80a0 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -178,7 +178,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
if options.ruby:
options.use_map = True
system.ruby = Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
@@ -187,8 +187,8 @@ for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
- system.cpu[i].icache_port = system.ruby.cpu_ruby_ports[i].port
- system.cpu[i].dcache_port = system.ruby.cpu_ruby_ports[i].port
+ system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
+ system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 4bd969be5..f0e072f90 100644
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 5f5703d4e..5018f2c18 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -78,20 +78,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index 15558a62d..c8b16fc5d 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -84,22 +84,23 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py
index 5b6e21f33..36999be5d 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -97,18 +97,8 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
@@ -122,6 +112,17 @@ def create_system(options, system, piobus, dma_devices):
no_mig_atomic = not \
options.allow_atomic_migration)
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 4a0391264..7e789d8e3 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -96,24 +96,25 @@ def create_system(options, system, piobus, dma_devices):
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache,
+ no_mig_atomic = not \
+ options.allow_atomic_migration)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache,
- no_mig_atomic = not \
- options.allow_atomic_migration)
-
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
diff --git a/configs/ruby/Network_test.py b/configs/ruby/Network_test.py
index 75ec9099e..308354f0f 100644
--- a/configs/ruby/Network_test.py
+++ b/configs/ruby/Network_test.py
@@ -83,20 +83,21 @@ def create_system(options, system, piobus, dma_devices):
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
using_network_tester = True)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 604bb7a73..3c58dfd2f 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -145,7 +145,7 @@ def create_system(options, system, piobus = None, dma_devices = []):
tracer = RubyTracer(),
mem_size = total_mem_size)
- ruby.cpu_ruby_ports = cpu_sequencers
+ ruby._cpu_ruby_ports = cpu_sequencers
ruby.random_seed = options.random_seed
return ruby
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 02:46:04 +0000