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-rw-r--r--configs/common/FSConfig.py12
-rw-r--r--configs/example/se.py14
-rw-r--r--configs/ruby/Ruby.py24
3 files changed, 49 insertions, 1 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index f54d63852..3c506c215 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010 ARM Limited
+# Copyright (c) 2010-2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -91,6 +91,8 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
self.console = binary('console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
@@ -183,6 +185,8 @@ def makeSparcSystem(mem_mode, mdesc = None):
self.hypervisor_desc_bin = binary('1up-hv.bin')
self.partition_desc_bin = binary('1up-md.bin')
+ self.system_port = self.membus.port
+
return self
def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
@@ -263,6 +267,8 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.terminal = Terminal()
self.vncserver = VncServer()
+ self.system_port = self.membus.port
+
return self
@@ -301,6 +307,8 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None):
self.console = binary('mips/console')
self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
+ self.system_port = self.membus.port
+
return self
def x86IOAddress(port):
@@ -320,6 +328,8 @@ def connectX86ClassicSystem(x86_sys):
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
+ x86_sys.system_port = x86_sys.membus.port
+
def connectX86RubySystem(x86_sys):
# North Bridge
x86_sys.piobus = Bus(bus_id=0)
diff --git a/configs/example/se.py b/configs/example/se.py
index 56737d6d5..0935a21a3 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2008 The Regents of The University of Michigan
# All rights reserved.
#
@@ -179,7 +191,9 @@ if options.ruby:
options.use_map = True
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+ system.system_port = system.ruby._sys_port_proxy.port
else:
+ system.system_port = system.membus.port
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index a07bea1bb..b2342eed4 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# All rights reserved.
@@ -82,6 +94,17 @@ def create_system(options, system, piobus = None, dma_devices = []):
print "Error: could not create sytem for ruby protocol %s" % protocol
raise
+ # Create a port proxy for connecting the system port. This is
+ # independent of the protocol and kept in the protocol-agnostic
+ # part (i.e. here).
+ sys_port_proxy = RubyPortProxy(version = 0,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem,
+ ruby_system = ruby)
+ # Give the system port proxy a SimObject parent without creating a
+ # full-fledged controller
+ system.sys_port_proxy = sys_port_proxy
+
#
# Set the network classes based on the command line options
#
@@ -159,4 +182,5 @@ def create_system(options, system, piobus = None, dma_devices = []):
ruby.profiler = ruby_profiler
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
+ ruby._sys_port_proxy = sys_port_proxy
ruby.random_seed = options.random_seed