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-rw-r--r--configs/common/Simulation.py16
-rw-r--r--configs/example/fs.py2
-rw-r--r--configs/example/se.py2
3 files changed, 6 insertions, 14 deletions
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index a67159a50..374ff3fc2 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -85,10 +85,6 @@ def run(options, root, testsys, cpu_class):
if not m5.build_env['FULL_SYSTEM']:
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus[i].clock = testsys.cpu[0].clock
- if options.caches:
- switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
- switch_cpus[i].connectMemPorts(testsys.membus)
root.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
@@ -108,19 +104,15 @@ def run(options, root, testsys, cpu_class):
switch_cpus[i].clock = testsys.cpu[0].clock
switch_cpus_1[i].clock = testsys.cpu[0].clock
- if options.caches:
- switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
- L1Cache(size = '64kB'))
- switch_cpus[i].connectMemPorts(testsys.membus)
- else:
+ if not options.caches:
# O3 CPU must have a cache to work.
switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
switch_cpus_1[i].connectMemPorts(testsys.membus)
- root.switch_cpus = switch_cpus
- root.switch_cpus_1 = switch_cpus_1
+ testsys.switch_cpus = switch_cpus
+ testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
@@ -219,5 +211,5 @@ def run(options, root, testsys, cpu_class):
if exit_cause == '':
exit_cause = exit_event.getCause()
- print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
+ print 'Exiting @ cycle %i because %s' % (m5.curTick(), exit_cause)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 180cd2719..a9f1d579a 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -95,7 +95,7 @@ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
np = options.num_cpus
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
for i in xrange(np):
- if options.caches and not options.standard_switch and not FutureClass:
+ if options.caches:
test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
test_sys.cpu[i].connectMemPorts(test_sys.membus)
diff --git a/configs/example/se.py b/configs/example/se.py
index 0a158244f..0944a030e 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -101,7 +101,7 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
system.physmem.port = system.membus.port
for i in xrange(np):
- if options.caches and not options.standard_switch and not FutureClass:
+ if options.caches:
system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
L1Cache(size = '64kB'))
system.cpu[i].connectMemPorts(system.membus)