diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/ruby/MESI_CMP_directory.py | 17 | ||||
| -rw-r--r-- | configs/ruby/MI_example.py | 4 | ||||
| -rw-r--r-- | configs/ruby/MOESI_CMP_directory.py | 17 | ||||
| -rw-r--r-- | configs/ruby/MOESI_CMP_token.py | 15 | ||||
| -rw-r--r-- | configs/ruby/MOESI_hammer.py | 10 |
5 files changed, 41 insertions, 22 deletions
diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py index 91a76497e..2f7faab52 100644 --- a/configs/ruby/MESI_CMP_directory.py +++ b/configs/ruby/MESI_CMP_directory.py @@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices): # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # + l2_bits = int(math.log(options.num_l2caches, 2)) + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, - assoc = options.l1i_assoc) + assoc = options.l1i_assoc, + start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) cpu_seq = RubySequencer(version = i, icache = l1i_cache, @@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices): sequencer = cpu_seq, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, - l2_select_num_bits = \ - math.log(options.num_l2caches, - 2)) + l2_select_num_bits = l2_bits) exec("system.l1_cntrl%d = l1_cntrl" % i) @@ -103,12 +105,15 @@ def create_system(options, system, piobus, dma_devices): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) + l2_index_start = block_size_bits + l2_bits + for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, - assoc = options.l2_assoc) + assoc = options.l2_assoc, + start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cacheMemory = l2_cache) diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py index 0e101d18f..82817d60a 100644 --- a/configs/ruby/MI_example.py +++ b/configs/ruby/MI_example.py @@ -60,6 +60,7 @@ def create_system(options, system, piobus, dma_devices): # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # @@ -68,7 +69,8 @@ def create_system(options, system, piobus, dma_devices): # config parameters. # cache = Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) # # Only one unified L1 cache exists. Can cache instructions and data. diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py index 11b65c397..ff7ea0cc5 100644 --- a/configs/ruby/MOESI_CMP_directory.py +++ b/configs/ruby/MOESI_CMP_directory.py @@ -68,15 +68,19 @@ def create_system(options, system, piobus, dma_devices): # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # + l2_bits = int(math.log(options.num_l2caches, 2)) + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, - assoc = options.l1i_assoc) + assoc = options.l1i_assoc, + start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) cpu_seq = RubySequencer(version = i, icache = l1i_cache, @@ -91,9 +95,7 @@ def create_system(options, system, piobus, dma_devices): sequencer = cpu_seq, L1IcacheMemory = l1i_cache, L1DcacheMemory = l1d_cache, - l2_select_num_bits = \ - math.log(options.num_l2caches, - 2)) + l2_select_num_bits = l2_bits) exec("system.l1_cntrl%d = l1_cntrl" % i) # @@ -102,12 +104,15 @@ def create_system(options, system, piobus, dma_devices): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) + l2_index_start = block_size_bits + l2_bits + for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, - assoc = options.l2_assoc) + assoc = options.l2_assoc, + start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cacheMemory = l2_cache) diff --git a/configs/ruby/MOESI_CMP_token.py b/configs/ruby/MOESI_CMP_token.py index 1e1190cae..72721058b 100644 --- a/configs/ruby/MOESI_CMP_token.py +++ b/configs/ruby/MOESI_CMP_token.py @@ -82,15 +82,18 @@ def create_system(options, system, piobus, dma_devices): # controller constructors are called before the network constructor # l2_bits = int(math.log(options.num_l2caches, 2)) + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, - assoc = options.l1i_assoc) + assoc = options.l1i_assoc, + start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) cpu_seq = RubySequencer(version = i, icache = l1i_cache, @@ -123,13 +126,15 @@ def create_system(options, system, piobus, dma_devices): cpu_sequencers.append(cpu_seq) l1_cntrl_nodes.append(l1_cntrl) + l2_index_start = block_size_bits + l2_bits + for i in xrange(options.num_l2caches): # # First create the Ruby objects associated with this cpu # l2_cache = L2Cache(size = options.l2_size, assoc = options.l2_assoc, - start_index_bit = l2_bits) + start_index_bit = l2_index_start) l2_cntrl = L2Cache_Controller(version = i, L2cacheMemory = l2_cache, @@ -158,9 +163,7 @@ def create_system(options, system, piobus, dma_devices): size = \ dir_size), memBuffer = mem_cntrl, - l2_select_num_bits = \ - math.log(options.num_l2caches, - 2)) + l2_select_num_bits = l2_bits) exec("system.dir_cntrl%d = dir_cntrl" % i) dir_cntrl_nodes.append(dir_cntrl) diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py index d0552263e..3804a58b1 100644 --- a/configs/ruby/MOESI_hammer.py +++ b/configs/ruby/MOESI_hammer.py @@ -78,17 +78,21 @@ def create_system(options, system, piobus, dma_devices): # Must create the individual controllers before the network to ensure the # controller constructors are called before the network constructor # + block_size_bits = int(math.log(options.cacheline_size, 2)) for i in xrange(options.num_cpus): # # First create the Ruby objects associated with this cpu # l1i_cache = L1Cache(size = options.l1i_size, - assoc = options.l1i_assoc) + assoc = options.l1i_assoc, + start_index_bit = block_size_bits) l1d_cache = L1Cache(size = options.l1d_size, - assoc = options.l1d_assoc) + assoc = options.l1d_assoc, + start_index_bit = block_size_bits) l2_cache = L2Cache(size = options.l2_size, - assoc = options.l2_assoc) + assoc = options.l2_assoc, + start_index_bit = block_size_bits) cpu_seq = RubySequencer(version = i, icache = l1i_cache, |