diff options
Diffstat (limited to 'configs')
-rw-r--r-- | configs/common/CacheConfig.py | 6 | ||||
-rw-r--r-- | configs/common/FSConfig.py | 14 | ||||
-rw-r--r-- | configs/dram/sweep.py | 2 | ||||
-rw-r--r-- | configs/example/memcheck.py | 4 | ||||
-rw-r--r-- | configs/example/memtest.py | 4 | ||||
-rw-r--r-- | configs/example/ruby_mem_test.py | 2 | ||||
-rw-r--r-- | configs/example/se.py | 2 | ||||
-rw-r--r-- | configs/ruby/Ruby.py | 2 | ||||
-rw-r--r-- | configs/splash2/cluster.py | 10 | ||||
-rw-r--r-- | configs/splash2/run.py | 4 |
10 files changed, 24 insertions, 26 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index f31b3d566..66fe491e1 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -65,14 +65,12 @@ def config_cache(options, system): if options.l2cache: # Provide a clock for the L2 and the L1-to-L2 bus here as they # are not connected using addTwoLevelCacheHierarchy. Use the - # same clock as the CPUs, and set the L1-to-L2 bus width to 32 - # bytes (256 bits). + # same clock as the CPUs. system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain, size=options.l2_size, assoc=options.l2_assoc) - system.tol2bus = CoherentXBar(clk_domain = system.cpu_clk_domain, - width = 32) + system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain) system.l2.cpu_side = system.tol2bus.master system.l2.mem_side = system.membus.slave diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index cfa6dee4d..e95fff424 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -50,7 +50,7 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci -class MemBus(CoherentXBar): +class MemBus(SystemXBar): badaddr_responder = BadAddr() default = Self.badaddr_responder.pio @@ -78,7 +78,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): self.tsunami = BaseTsunami() # Create the io bus to connect all device ports - self.iobus = NoncoherentXBar() + self.iobus = IOXBar() self.tsunami.attachIO(self.iobus) self.tsunami.ide.pio = self.iobus.master @@ -143,7 +143,7 @@ def makeSparcSystem(mem_mode, mdesc=None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentXBar() + self.iobus = IOXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.t1000 = T1000() @@ -205,7 +205,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentXBar() + self.iobus = IOXBar() self.membus = MemBus() self.membus.badaddr_responder.warn_access = "warn" self.bridge = Bridge(delay='50ns') @@ -311,7 +311,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): # generic system mdesc = SysConfig() self.readfile = mdesc.script() - self.iobus = NoncoherentXBar() + self.iobus = IOXBar() self.membus = MemBus() self.bridge = Bridge(delay='50ns') self.mem_ranges = [AddrRange('1GB')] @@ -358,7 +358,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): x86_sys.membus = MemBus() # North Bridge - x86_sys.iobus = NoncoherentXBar() + x86_sys.iobus = IOXBar() x86_sys.bridge = Bridge(delay='50ns') x86_sys.bridge.master = x86_sys.iobus.slave x86_sys.bridge.slave = x86_sys.membus.master @@ -394,7 +394,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): def connectX86RubySystem(x86_sys): # North Bridge - x86_sys.iobus = NoncoherentXBar() + x86_sys.iobus = IOXBar() # add the ide to the list of dma devices that later need to attach to # dma controllers diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index 18a58b2da..f0b20dcc5 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -84,7 +84,7 @@ if args: # start with the system itself, using a multi-layer 1.5 GHz # crossbar, delivering 64 bytes / 5 cycles (one header cycle) # which amounts to 19.2 GByte/s per layer and thus per port -system = System(membus = NoncoherentXBar(width = 16)) +system = System(membus = IOXBar(width = 16)) system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = VoltageDomain(voltage = '1V')) diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py index 4f85223d9..f0bc26e32 100644 --- a/configs/example/memcheck.py +++ b/configs/example/memcheck.py @@ -243,7 +243,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache): if level != 0: # Create a crossbar and add it to the subsystem, note that # we do this even with a single element on this level - xbar = CoherentXBar(width = 32) + xbar = L2XBar(width = 32) subsys.xbar = xbar if next_cache: xbar.master = next_cache.cpu_side @@ -269,7 +269,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache): if ntesters > 1: # Create a crossbar and add it to the subsystem - xbar = CoherentXBar(width = 32) + xbar = L2XBar(width = 32) subsys.xbar = xbar xbar.master = next_cache.cpu_side for tester, checker in zip(testers, checkers): diff --git a/configs/example/memtest.py b/configs/example/memtest.py index 6c1e657e4..9a66320d8 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -233,7 +233,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache): if level != 0: # Create a crossbar and add it to the subsystem, note that # we do this even with a single element on this level - xbar = CoherentXBar(width = 32) + xbar = L2XBar() subsys.xbar = xbar if next_cache: xbar.master = next_cache.cpu_side @@ -258,7 +258,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache): if ntesters > 1: # Create a crossbar and add it to the subsystem - xbar = CoherentXBar(width = 32) + xbar = L2XBar() subsys.xbar = xbar xbar.master = next_cache.cpu_side for tester in testers: diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index f5e6d2a82..e2887410f 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -106,7 +106,7 @@ cpus = [ MemTest(atomic = False, system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar(), + funcbus = IOXBar(), clk_domain = SrcClockDomain(clock = options.sys_clock), mem_ranges = [AddrRange(options.mem_size)]) diff --git a/configs/example/se.py b/configs/example/se.py index 3f51acdeb..a582d2976 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -265,7 +265,7 @@ if options.ruby: system.cpu[i].dtb.walker.port = ruby_port.slave else: MemClass = Simulation.setMemClass(options) - system.membus = CoherentXBar() + system.membus = SystemXBar() system.system_port = system.membus.slave CacheConfig.config_cache(options, system) MemConfig.config_mem(options, system) diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index e0d53fd6c..1fa969782 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -116,7 +116,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options): crossbar = None if len(system.mem_ranges) > 1: - crossbar = NoncoherentXBar() + crossbar = IOXBar() crossbars.append(crossbar) dir_cntrl.memory = crossbar.slave diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py index b17c8877e..9fafcb70c 100644 --- a/configs/splash2/cluster.py +++ b/configs/splash2/cluster.py @@ -171,7 +171,7 @@ if options.timing: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -184,7 +184,7 @@ elif options.detailed: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -197,7 +197,7 @@ else: for j in xrange(options.numclusters): clusters[j].id = j for cluster in clusters: - cluster.clusterbus = CoherentXBar(clock=busFrequency) + cluster.clusterbus = L2XBar(clock=busFrequency) all_l1buses += [cluster.clusterbus] cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id, clock=options.frequency) @@ -211,10 +211,10 @@ else: # ---------------------- system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem = SimpleMemory(), - membus = CoherentXBar(clock = busFrequency)) + membus = SystemXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentXBar(clock = busFrequency) +system.toL2bus = L2XBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- diff --git a/configs/splash2/run.py b/configs/splash2/run.py index d542a9437..14e5f47d4 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -196,10 +196,10 @@ else: # Create a system, and add system wide objects # ---------------------- system = System(cpu = cpus, physmem = SimpleMemory(), - membus = CoherentXBar(clock = busFrequency)) + membus = SystemXBar(clock = busFrequency)) system.clock = '1GHz' -system.toL2bus = CoherentXBar(clock = busFrequency) +system.toL2bus = L2XBar(clock = busFrequency) system.l2 = L2(size = options.l2size, assoc = 8) # ---------------------- |