diff options
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/example/ruby.config | 190 | ||||
| -rw-r--r-- | configs/example/ruby_se.py | 172 |
2 files changed, 362 insertions, 0 deletions
diff --git a/configs/example/ruby.config b/configs/example/ruby.config new file mode 100644 index 000000000..1297ae6a3 --- /dev/null +++ b/configs/example/ruby.config @@ -0,0 +1,190 @@ +//Default parameters, taken from /athitos/export/08spr_ee382a/sanchezd/runs/gen-scripts/ruby.defaults + +//General config +g_DEADLOCK_THRESHOLD: 20000000 +RANDOMIZATION: false +g_tester_length: 0 +SIMICS_RUBY_MULTIPLIER: 1 +OPAL_RUBY_MULTIPLIER: 1 +TRANSACTION_TRACE_ENABLED: false +USER_MODE_DATA_ONLY: false +PROFILE_HOT_LINES: false +PROFILE_ALL_INSTRUCTIONS: false +PRINT_INSTRUCTION_TRACE: false +g_DEBUG_CYCLE: 0 +PERFECT_MEMORY_SYSTEM: false +PERFECT_MEMORY_SYSTEM_LATENCY: 0 +DATA_BLOCK: false + +// Line, page sizes +g_DATA_BLOCK_BYTES: 64 +g_PAGE_SIZE_BYTES: 8192 + + +g_REPLACEMENT_POLICY: PSEDUO_LRU +// For all caches (sic) + +// L1 config +// 32KB, 4-way SA +L1_CACHE_ASSOC: 4 +L1_CACHE_NUM_SETS_BITS: 7 +// Single-cycle latency, hits take fastpath +SEQUENCER_TO_CONTROLLER_LATENCY: 1 +REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false +// L1->L2 delays +L1_REQUEST_LATENCY: 1 +L1_RESPONSE_LATENCY: 1 + +// L2 parameters +// 4 MB, 16-way SA +L2_CACHE_ASSOC: 16 +L2_CACHE_NUM_SETS_BITS: 12 +MAP_L2BANKS_TO_LOWEST_BITS: false +// Bank latencies +L2_RESPONSE_LATENCY: 10 +L2_TAG_LATENCY: 5 + + +// Directory latencies +// The one that counts, we have perfect dirs +DIRECTORY_CACHE_LATENCY: 6 +// should not be used, but just in case... +DIRECTORY_LATENCY: 6 + +// Simple network parameters +// external links +NETWORK_LINK_LATENCY: 1 +// intra-chip links +ON_CHIP_LINK_LATENCY: 1 + +// General latencies +RECYCLE_LATENCY: 1 +//Used in MessageBuffer, also MSI_MOSI_CMP dir controller + + +// Unused parameters, good to define them to really weird things just in case +NULL_LATENCY: 100000 +// Only SMP and token CMP protocols +ISSUE_LATENCY: 100000 +// Only SMP, example protocols +CACHE_RESPONSE_LATENCY: 100000 +// Only SMP protocols +COPY_HEAD_LATENCY: 100000 +// In no protocols or ruby code +L2_RECYCLE_LATENCY: 100000 +// In no protocols or ruby code +TIMER_LATENCY: 100000 +// Not used +TBE_RESPONSE_LATENCY: 100000 +// Not used +PERIODIC_TIMER_WAKEUPS: false +// Not used +BLOCK_STC: false +// Not used +SINGLE_ACCESS_L2_BANKS: false +// Not used + +// Main memory latency +MEMORY_RESPONSE_LATENCY_MINUS_2: 448 //not used in _m, see below + +PROFILE_EXCEPTIONS: false +PROFILE_XACT: false +PROFILE_NONXACT: true +XACT_DEBUG: false +XACT_DEBUG_LEVEL: 1 +XACT_MEMORY: false +XACT_ENABLE_TOURMALINE: false +XACT_NUM_CURRENT: 0 +XACT_LAST_UPDATE: 0 +XACT_ISOLATION_CHECK: false +PERFECT_FILTER: true +READ_WRITE_FILTER: Perfect_ +PERFECT_VIRTUAL_FILTER: true +VIRTUAL_READ_WRITE_FILTER: Perfect_ +PERFECT_SUMMARY_FILTER: true +SUMMARY_READ_WRITE_FILTER: Perfect_ +XACT_EAGER_CD: true +XACT_LAZY_VM: false +XACT_CONFLICT_RES: BASE +XACT_COMMIT_TOKEN_LATENCY: 0 +XACT_NO_BACKOFF: false +XACT_LOG_BUFFER_SIZE: 0 +XACT_STORE_PREDICTOR_HISTORY: 0 +XACT_STORE_PREDICTOR_ENTRIES: 0 +XACT_STORE_PREDICTOR_THRESHOLD: 0 +XACT_FIRST_ACCESS_COST: 0 +XACT_FIRST_PAGE_ACCESS_COST: 0 +ENABLE_MAGIC_WAITING: false +ENABLE_WATCHPOINT: false +XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false +ATMTP_ENABLED: false +ATMTP_ABORT_ON_NON_XACT_INST: false +ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false +ATMTP_XACT_MAX_STORES: 0 +ATMTP_DEBUG_LEVEL: 0 +XACT_LENGTH: 0 +XACT_SIZE: 0 +ABORT_RETRY_TIME: 0 + + +// Allowed parallelism in controllers +L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 +L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 1000 +DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 1000 +g_SEQUENCER_OUTSTANDING_REQUESTS: 16 + +//TBEs == MSHRs (global) +NUMBER_OF_TBES: 128 +NUMBER_OF_L1_TBES: 32 +// unused in CMP protocols +NUMBER_OF_L2_TBES: 32 +// unused in CMP protocols + + +// TSO & WBuffer params (unused) +FINITE_BUFFERING: false +FINITE_BUFFER_SIZE: 3 +PROCESSOR_BUFFER_SIZE: 10 +PROTOCOL_BUFFER_SIZE: 32 +TSO: false + +// General network params +g_endpoint_bandwidth: 10000 +g_adaptive_routing: true +NUMBER_OF_VIRTUAL_NETWORKS: 5 +FAN_OUT_DEGREE: 4 +// for HIERARCHICAL_SWITCH + + +// Detailed Memory Controller Params (only used in _m protocols) +MEM_BUS_CYCLE_MULTIPLIER: 5 +BANKS_PER_RANK: 8 +RANKS_PER_DIMM: 2 +DIMMS_PER_CHANNEL: 2 +BANK_BIT_0: 8 +RANK_BIT_0: 11 +DIMM_BIT_0: 12 + +BANK_QUEUE_SIZE: 12 +BANK_BUSY_TIME: 22 +RANK_RANK_DELAY: 2 +READ_WRITE_DELAY: 3 +BASIC_BUS_BUSY_TIME: 3 +MEM_CTL_LATENCY: 20 +REFRESH_PERIOD: 3120 +TFAW: 0 +//flip a coin to delay requests by one cycle, introduces non-determinism +MEM_RANDOM_ARBITRATE: 50 +MEM_FIXED_DELAY: 0 + + +//Configuration-specific parameters +g_NUM_PROCESSORS: 1 +g_NUM_CHIPS: 1 +g_PROCS_PER_CHIP: 1 +g_NUM_L2_BANKS: 1 +g_NUM_MEMORIES: 4 +g_PRINT_TOPOLOGY: true +g_GARNET_NETWORK: true +g_DETAIL_NETWORK: true +g_FLIT_SIZE: 8 diff --git a/configs/example/ruby_se.py b/configs/example/ruby_se.py new file mode 100644 index 000000000..488ccb64a --- /dev/null +++ b/configs/example/ruby_se.py @@ -0,0 +1,172 @@ +# Copyright (c) 2006-2008 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt + +# Simple test script +# +# "m5 test.py" + +import m5 + +if m5.build_env['FULL_SYSTEM']: + m5.panic("This script requires syscall emulation mode (*_SE).") + +from m5.objects import * +import os, optparse, sys +from os.path import join as joinpath +m5.AddToPath('../common') +import Simulation +#from Caches import * +from cpu2000 import * + +# Get paths we might need. It's expected this file is in m5/configs/example. +config_path = os.path.dirname(os.path.abspath(__file__)) +config_root = os.path.dirname(config_path) +m5_root = os.path.dirname(config_root) + +parser = optparse.OptionParser() + +# Benchmark options +parser.add_option("-c", "--cmd", + default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), + help="The binary to run in syscall emulation mode.") +parser.add_option("-o", "--options", default="", + help='The options to pass to the binary, use " " around the entire string') +parser.add_option("-i", "--input", default="", help="Read stdin from a file.") +parser.add_option("--output", default="", help="Redirect stdout to a file.") +parser.add_option("--errout", default="", help="Redirect stderr to a file.") +parser.add_option("--ruby-debug", action="store_true") +parser.add_option("--ruby-debug-file", default="", help="Ruby debug out file (stdout if blank)") + +execfile(os.path.join(config_root, "common", "Options.py")) + +(options, args) = parser.parse_args() + +if args: + print "Error: script doesn't take any positional arguments" + sys.exit(1) + +if options.bench: + try: + if m5.build_env['TARGET_ISA'] != 'alpha': + print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time" + sys.exit(1) + exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench) + process = workload.makeLiveProcess() + except: + print >>sys.stderr, "Unable to find workload for %s" % options.bench + sys.exit(1) +else: + process = LiveProcess() + process.executable = options.cmd + process.cmd = [options.cmd] + options.options.split() + + +if options.input != "": + process.input = options.input +if options.output != "": + process.output = options.output +if options.errout != "": + process.errout = options.errout + +if options.detailed: + #check for SMT workload + workloads = options.cmd.split(';') + if len(workloads) > 1: + process = [] + smt_idx = 0 + inputs = [] + outputs = [] + errouts = [] + + if options.input != "": + inputs = options.input.split(';') + if options.output != "": + outputs = options.output.split(';') + if options.errout != "": + errouts = options.errout.split(';') + + for wrkld in workloads: + smt_process = LiveProcess() + smt_process.executable = wrkld + smt_process.cmd = wrkld + " " + options.options + if inputs and inputs[smt_idx]: + smt_process.input = inputs[smt_idx] + if outputs and outputs[smt_idx]: + smt_process.output = outputs[smt_idx] + if errouts and errouts[smt_idx]: + smt_process.errout = errouts[smt_idx] + process += [smt_process, ] + smt_idx += 1 + +(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) + +CPUClass.clock = '1GHz' + +np = options.num_cpus + +rubymem = RubyMemory( + range = AddrRange("512MB"), + clock = "1GHz", + num_cpus = np, + libruby_file = "src/mem/ruby/amd64-linux/generated/MOESI_CMP_directory/bin/libruby.so", + config_file = "ruby.config", + stats_file = "m5out/ruby.stats" +) + +if options.ruby_debug == True: + rubymem.debug = True + rubymem.debug_file = options.ruby_debug_file + +system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], + physmem = rubymem) + +if options.l2cache: + print "Error: -l2cache incompatible with ruby, must configure it ruby-style" + sys.exit(1) + +if options.caches: + print "Error: -caches incompatible with ruby, must configure it ruby-style" + sys.exit(1) + +for i in xrange(np): + system.cpu[i].connectMemPorts(system.physmem) + + + '''process = LiveProcess() + process.executable = options.cmd + process.cmd = [options.cmd, str(i)] + ''' + system.cpu[i].workload = process + + if options.fastmem: + system.cpu[i].physmem_port = system.physmem.port + + +root = Root(system = system) + +Simulation.run(options, root, system, FutureClass) |