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-rw-r--r--configs/common/Caches.py8
-rw-r--r--configs/common/O3_ARM_v7a.py8
-rw-r--r--configs/example/memcheck.py6
-rw-r--r--configs/example/memtest.py6
-rw-r--r--configs/splash2/cluster.py4
-rw-r--r--configs/splash2/run.py4
6 files changed, 18 insertions, 18 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index cfb873b5e..0a3c56297 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -46,7 +46,7 @@ from m5.objects import *
# starting point, and specific parameters can be overridden in the
# specific instantiations.
-class L1Cache(BaseCache):
+class L1Cache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
@@ -59,7 +59,7 @@ class L1_ICache(L1Cache):
class L1_DCache(L1Cache):
pass
-class L2Cache(BaseCache):
+class L2Cache(Cache):
assoc = 8
hit_latency = 20
response_latency = 20
@@ -67,7 +67,7 @@ class L2Cache(BaseCache):
tgts_per_mshr = 12
write_buffers = 8
-class IOCache(BaseCache):
+class IOCache(Cache):
assoc = 8
hit_latency = 50
response_latency = 50
@@ -76,7 +76,7 @@ class IOCache(BaseCache):
tgts_per_mshr = 12
forward_snoops = False
-class PageTableWalkerCache(BaseCache):
+class PageTableWalkerCache(Cache):
assoc = 2
hit_latency = 2
response_latency = 2
diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index dbfdf6c41..9f250f57d 100644
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -142,7 +142,7 @@ class O3_ARM_v7a_3(DerivO3CPU):
branchPred = O3_ARM_v7a_BP()
# Instruction Cache
-class O3_ARM_v7a_ICache(BaseCache):
+class O3_ARM_v7a_ICache(Cache):
hit_latency = 1
response_latency = 1
mshrs = 2
@@ -153,7 +153,7 @@ class O3_ARM_v7a_ICache(BaseCache):
is_read_only = True
# Data Cache
-class O3_ARM_v7a_DCache(BaseCache):
+class O3_ARM_v7a_DCache(Cache):
hit_latency = 2
response_latency = 2
mshrs = 6
@@ -164,7 +164,7 @@ class O3_ARM_v7a_DCache(BaseCache):
# TLB Cache
# Use a cache as a L2 TLB
-class O3_ARM_v7aWalkCache(BaseCache):
+class O3_ARM_v7aWalkCache(Cache):
hit_latency = 4
response_latency = 4
mshrs = 6
@@ -176,7 +176,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
is_read_only = True
# L2 Cache
-class O3_ARM_v7aL2(BaseCache):
+class O3_ARM_v7aL2(Cache):
hit_latency = 12
response_latency = 12
mshrs = 16
diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py
index ca2659ed0..18c75376f 100644
--- a/configs/example/memcheck.py
+++ b/configs/example/memcheck.py
@@ -152,9 +152,9 @@ for t, m in zip(testerspec, multiplier):
numtesters += t * m
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index a51bd2796..08f134533 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -175,9 +175,9 @@ else:
sys.exit(1)
# Define a prototype L1 cache that we scale for all successive levels
-proto_l1 = BaseCache(size = '32kB', assoc = 4,
- hit_latency = 1, response_latency = 1,
- tgts_per_mshr = 8)
+proto_l1 = Cache(size = '32kB', assoc = 4,
+ hit_latency = 1, response_latency = 1,
+ tgts_per_mshr = 8)
if options.blocking:
proto_l1.mshrs = 1
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index 9fafcb70c..5991e7428 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -137,7 +137,7 @@ class Water_spatial(LiveProcess):
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
@@ -146,7 +146,7 @@ class L1(BaseCache):
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 14e5f47d4..bf7d1331e 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -158,7 +158,7 @@ class Water_spatial(LiveProcess):
# Base L1 Cache Definition
# ====================
-class L1(BaseCache):
+class L1(Cache):
latency = options.l1latency
mshrs = 12
tgts_per_mshr = 8
@@ -167,7 +167,7 @@ class L1(BaseCache):
# Base L2 Cache Definition
# ----------------------
-class L2(BaseCache):
+class L2(Cache):
latency = options.l2latency
mshrs = 92
tgts_per_mshr = 16