1 files changed, 28 insertions, 27 deletions

diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index d921bd148..bf7c35cad 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -36,7 +36,7 @@
 #include "base/cprintf.hh"
 #include "base/trace.hh"
 
-#include "arch/alpha/faults.hh"
+#include "arch/faults.hh"
 #include "cpu/exetrace.hh"
 #include "mem/mem_req.hh"
 
@@ -45,6 +45,7 @@
 #include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
+using namespace TheISA;
 
 #define NOHASH
 #ifndef NOHASH
@@ -67,7 +68,7 @@ template <class Impl>
 BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
                                Addr pred_PC, InstSeqNum seq_num,
                                FullCPU *cpu)
-    : staticInst(machInst), traceData(NULL), cpu(cpu), xc(cpu->xcBase())
+    : staticInst(machInst), traceData(NULL), cpu(cpu), cpuXC(cpu->cpuXCBase())
 {
     seqNum = seq_num;
 
@@ -79,7 +80,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
 }
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
     : staticInst(_staticInst), traceData(NULL)
 {
     initVars();
@@ -113,7 +114,7 @@ BaseDynInst<Impl>::initVars()
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
-    fault = Unimplemented_Opcode_Fault;
+    fault = new UnimplementedOpcodeFault;
 
     ++instcount;
 
@@ -138,16 +139,16 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     // state.
 
     // Generate a MemReq so we can translate the effective address.
-    MemReqPtr req = new MemReq(addr, xc, 1, flags);
+    MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), 1, flags);
     req->asid = asid;
 
     // Prefetches never cause faults.
-    fault = No_Fault;
+    fault = NoFault;
 
     // note this is a local, not BaseDynInst::fault
-    Fault trans_fault = xc->translateDataReadReq(req);
+    Fault trans_fault = cpuXC->translateDataReadReq(req);
 
-    if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // It's a valid address to cacheable space.  Record key MemReq
         // parameters so we can generate another one just like it for
         // the timing access without calling translate() again (which
@@ -183,12 +184,12 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
     // will casue a TLB miss trap if necessary... not sure whether
     // that's the best thing to do or not.  We don't really need the
     // MemReq otherwise, since wh64 has no functional effect.
-    MemReqPtr req = new MemReq(addr, xc, size, flags);
+    MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), size, flags);
     req->asid = asid;
 
-    fault = xc->translateDataWriteReq(req);
+    fault = cpuXC->translateDataWriteReq(req);
 
-    if (fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // Record key MemReq parameters so we can generate another one
         // just like it for the timing access without calling translate()
         // again (which might mess up the TLB).
@@ -211,18 +212,18 @@ template <class Impl>
 Fault
 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 {
-    MemReqPtr req = new MemReq(src, xc, 64);
+    MemReqPtr req = new MemReq(src, cpuXC->getProxy(), 64);
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(req);
+    Fault fault = cpuXC->translateDataReadReq(req);
 
-    if (fault == No_Fault) {
-        xc->copySrcAddr = src;
-        xc->copySrcPhysAddr = req->paddr;
+    if (fault == NoFault) {
+        cpuXC->copySrcAddr = src;
+        cpuXC->copySrcPhysAddr = req->paddr;
     } else {
-        xc->copySrcAddr = 0;
-        xc->copySrcPhysAddr = 0;
+        cpuXC->copySrcAddr = 0;
+        cpuXC->copySrcPhysAddr = 0;
     }
     return fault;
 }
@@ -235,18 +236,18 @@ Fault
 BaseDynInst<Impl>::copy(Addr dest)
 {
     uint8_t data[64];
-    FunctionalMemory *mem = xc->mem;
-    assert(xc->copySrcPhysAddr || xc->misspeculating());
-    MemReqPtr req = new MemReq(dest, xc, 64);
+    FunctionalMemory *mem = cpuXC->mem;
+    assert(cpuXC->copySrcPhysAddr || cpuXC->misspeculating());
+    MemReqPtr req = new MemReq(dest, cpuXC->getProxy(), 64);
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(req);
+    Fault fault = cpuXC->translateDataWriteReq(req);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         Addr dest_addr = req->paddr;
         // Need to read straight from memory since we have more than 8 bytes.
-        req->paddr = xc->copySrcPhysAddr;
+        req->paddr = cpuXC->copySrcPhysAddr;
         mem->read(req, data);
         req->paddr = dest_addr;
         mem->write(req, data);
@@ -292,7 +293,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 #if 0
         panic("unaligned access. Cycle = %n", curTick);
 #endif
-        return No_Fault;
+        return NoFault;
     }
 
     MemReqPtr req = new MemReq(addr, thread, nbytes);
@@ -303,7 +304,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 
       case Write:
         fault = spec_mem->write(req, (uint8_t *)p);
-        if (fault != No_Fault)
+        if (fault != NoFault)
             break;
 
         specMemWrite = true;
@@ -325,7 +326,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
         break;
 
       default:
-        fault = Machine_Check_Fault;
+        fault = genMachineCheckFault();
         break;
     }