1 files changed, 41 insertions, 15 deletions

diff --git a/cpu/beta_cpu/alpha_dyn_inst_impl.hh b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
index 8311067db..4a3ae99d4 100644
--- a/cpu/beta_cpu/alpha_dyn_inst_impl.hh
+++ b/cpu/beta_cpu/alpha_dyn_inst_impl.hh
@@ -4,42 +4,68 @@
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
                                  InstSeqNum seq_num, FullCPU *cpu)
-    : BaseDynInst<AlphaSimpleImpl>(inst, PC, Pred_PC, seq_num, cpu)
+    : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < this->staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = this->staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = this->staticInst->srcRegIdx(i);
+        this->_readySrcRegIdx[i] = 0;
+    }
+
 }
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
-    : BaseDynInst<AlphaSimpleImpl>(_staticInst)
+    : BaseDynInst<Impl>(_staticInst)
 {
+    // Make sure to have the renamed register entries set to the same
+    // as the normal register entries.  It will allow the IQ to work
+    // without any modifications.
+    for (int i = 0; i < _staticInst->numDestRegs(); i++)
+    {
+        _destRegIdx[i] = _staticInst->destRegIdx(i);
+    }
+
+    for (int i = 0; i < _staticInst->numSrcRegs(); i++)
+    {
+        _srcRegIdx[i] = _staticInst->srcRegIdx(i);
+    }
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readUniq()
 {
-    return cpu->readUniq();
+    return this->cpu->readUniq();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setUniq(uint64_t val)
 {
-    cpu->setUniq(val);
+    this->cpu->setUniq(val);
 }
 
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readFpcr()
 {
-    return cpu->readFpcr();
+    return this->cpu->readFpcr();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setFpcr(uint64_t val)
 {
-    cpu->setFpcr(val);
+    this->cpu->setFpcr(val);
 }
 
 #ifdef FULL_SYSTEM
@@ -47,63 +73,63 @@ template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
 {
-    return cpu->readIpr(idx, fault);
+    return this->cpu->readIpr(idx, fault);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
 {
-    return cpu->setIpr(idx, val);
+    return this->cpu->setIpr(idx, val);
 }
 
 template <class Impl>
 Fault
 AlphaDynInst<Impl>::hwrei()
 {
-    return cpu->hwrei();
+    return this->cpu->hwrei();
 }
 
 template <class Impl>
 int
 AlphaDynInst<Impl>::readIntrFlag()
 {
-return cpu->readIntrFlag();
+return this->cpu->readIntrFlag();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::setIntrFlag(int val)
 {
-    cpu->setIntrFlag(val);
+    this->cpu->setIntrFlag(val);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::inPalMode()
 {
-    return cpu->inPalMode();
+    return this->cpu->inPalMode();
 }
 
 template <class Impl>
 void
 AlphaDynInst<Impl>::trap(Fault fault)
 {
-    cpu->trap(fault);
+    this->cpu->trap(fault);
 }
 
 template <class Impl>
 bool
 AlphaDynInst<Impl>::simPalCheck(int palFunc)
 {
-    return cpu->simPalCheck(palFunc);
+    return this->cpu->simPalCheck(palFunc);
 }
 #else
 template <class Impl>
 void
 AlphaDynInst<Impl>::syscall()
 {
-    cpu->syscall();
+    this->cpu->syscall();
 }
 #endif