diff options
Diffstat (limited to 'cpu/beta_cpu/regfile.hh')
| -rw-r--r-- | cpu/beta_cpu/regfile.hh | 373 |
1 files changed, 195 insertions, 178 deletions
diff --git a/cpu/beta_cpu/regfile.hh b/cpu/beta_cpu/regfile.hh index a81ed63bc..c9d1b092f 100644 --- a/cpu/beta_cpu/regfile.hh +++ b/cpu/beta_cpu/regfile.hh @@ -1,18 +1,26 @@ -#ifndef __REGFILE_HH__ -#define __REGFILE_HH__ +#ifndef __CPU_BETA_CPU_REGFILE_HH__ +#define __CPU_BETA_CPU_REGFILE_HH__ // @todo: Destructor #include "arch/alpha/isa_traits.hh" +#include "base/trace.hh" #include "cpu/beta_cpu/comm.hh" -#include "base/trace.hh" +#ifdef FULL_SYSTEM +#include "kern/kernel_stats.hh" +#include "arch/alpha/ev5.hh" + +using namespace EV5; +#endif // This really only depends on the ISA, and not the Impl. It might be nicer // to see if I can make it depend on nothing... // Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA, // and should go in the AlphaFullCPU. +extern void debug_break(); + template <class Impl> class PhysRegFile { @@ -27,6 +35,7 @@ class PhysRegFile //be private eventually with some accessor functions. public: typedef typename Impl::ISA ISA; + typedef typename Impl::FullCPU FullCPU; PhysRegFile(unsigned _numPhysicalIntRegs, unsigned _numPhysicalFloatRegs); @@ -177,6 +186,7 @@ class PhysRegFile #ifdef FULL_SYSTEM uint64_t readIpr(int idx, Fault &fault); Fault setIpr(int idx, uint64_t val); + InternalProcReg *getIpr() { return ipr; } int readIntrFlag() { return intrflag; } void setIntrFlag(int val) { intrflag = val; } #endif @@ -196,7 +206,21 @@ class PhysRegFile Addr pc; // program counter Addr npc; // next-cycle program counter +#ifdef FULL_SYSTEM private: + // This is ISA specifc stuff; remove it eventually once ISAImpl is used + IntReg palregs[NumIntRegs]; // PAL shadow registers + InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs + int intrflag; // interrupt flag + bool pal_shadow; // using pal_shadow registers +#endif + + private: + FullCPU *cpu; + + public: + void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } + unsigned numPhysicalIntRegs; unsigned numPhysicalFloatRegs; }; @@ -269,46 +293,42 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) case ISA::IPR_IPLR: case ISA::IPR_INTID: case ISA::IPR_PMCTR: - // no side-effect - retval = ipr[idx]; - break; + // no side-effect + retval = ipr[idx]; + break; case ISA::IPR_CC: - retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= curTick & ULL(0x00000000ffffffff); - break; + retval |= ipr[idx] & ULL(0xffffffff00000000); + retval |= curTick & ULL(0x00000000ffffffff); + break; case ISA::IPR_VA: - // SFX: unlocks interrupt status registers - retval = ipr[idx]; - - if (!misspeculating()) - regs.intrlock = false; - break; + retval = ipr[idx]; + break; case ISA::IPR_VA_FORM: case ISA::IPR_MM_STAT: case ISA::IPR_IFAULT_VA_FORM: case ISA::IPR_EXC_MASK: case ISA::IPR_EXC_SUM: - retval = ipr[idx]; - break; + retval = ipr[idx]; + break; case ISA::IPR_DTB_PTE: - { - ISA::PTE &pte = dtb->index(!misspeculating()); - - retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; - retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; - retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; - retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; - retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; - retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; - retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; - } - break; - - // write only registers + { + typename ISA::PTE &pte = cpu->dtb->index(1); + + retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; + retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; + retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12; + retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1; + retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2; + retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4; + retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57; + } + break; + + // write only registers case ISA::IPR_HWINT_CLR: case ISA::IPR_SL_XMIT: case ISA::IPR_DC_FLUSH: @@ -318,22 +338,19 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault) case ISA::IPR_DTB_IAP: case ISA::IPR_ITB_IA: case ISA::IPR_ITB_IAP: - fault = Unimplemented_Opcode_Fault; - break; + fault = Unimplemented_Opcode_Fault; + break; default: - // invalid IPR - fault = Unimplemented_Opcode_Fault; - break; + // invalid IPR + fault = Unimplemented_Opcode_Fault; + break; } return retval; } -#ifdef DEBUG -// Cause the simulator to break when changing to the following IPL -int break_ipl = -1; -#endif +extern int break_ipl; template <class Impl> Fault @@ -341,9 +358,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) { uint64_t old; - if (misspeculating()) - return No_Fault; - switch (idx) { case ISA::IPR_PALtemp0: case ISA::IPR_PALtemp1: @@ -372,222 +386,225 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) case ISA::IPR_IC_PERR_STAT: case ISA::IPR_DC_PERR_STAT: case ISA::IPR_PMCTR: - // write entire quad w/ no side-effect - ipr[idx] = val; - break; + // write entire quad w/ no side-effect + ipr[idx] = val; + break; case ISA::IPR_CC_CTL: - // This IPR resets the cycle counter. We assume this only - // happens once... let's verify that. - assert(ipr[idx] == 0); - ipr[idx] = 1; - break; + // This IPR resets the cycle counter. We assume this only + // happens once... let's verify that. + assert(ipr[idx] == 0); + ipr[idx] = 1; + break; case ISA::IPR_CC: - // This IPR only writes the upper 64 bits. It's ok to write - // all 64 here since we mask out the lower 32 in rpcc (see - // isa_desc). - ipr[idx] = val; - break; + // This IPR only writes the upper 64 bits. It's ok to write + // all 64 here since we mask out the lower 32 in rpcc (see + // isa_desc). + ipr[idx] = val; + break; case ISA::IPR_PALtemp23: - // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; - kernelStats.context(old, val); - break; + // write entire quad w/ no side-effect + old = ipr[idx]; + ipr[idx] = val; +// kernelStats.context(old, val); + break; case ISA::IPR_DTB_PTE: - // write entire quad w/ no side-effect, tag is forthcoming - ipr[idx] = val; - break; + // write entire quad w/ no side-effect, tag is forthcoming + ipr[idx] = val; + break; case ISA::IPR_EXC_ADDR: - // second least significant bit in PC is always zero - ipr[idx] = val & ~2; - break; + // second least significant bit in PC is always zero + ipr[idx] = val & ~2; + break; case ISA::IPR_ASTRR: case ISA::IPR_ASTER: - // only write least significant four bits - privilege mask - ipr[idx] = val & 0xf; - break; + // only write least significant four bits - privilege mask + ipr[idx] = val & 0xf; + break; case ISA::IPR_IPLR: #ifdef DEBUG - if (break_ipl != -1 && break_ipl == (val & 0x1f)) - debug_break(); + if (break_ipl != -1 && break_ipl == (val & 0x1f)) + debug_break(); #endif - // only write least significant five bits - interrupt level - ipr[idx] = val & 0x1f; - kernelStats.swpipl(ipr[idx]); - break; + // only write least significant five bits - interrupt level + ipr[idx] = val & 0x1f; +// kernelStats.swpipl(ipr[idx]); + break; case ISA::IPR_DTB_CM: - kernelStats.mode((val & 0x18) != 0); +// if (val & 0x18) +// kernelStats->mode(Kernel::user); +// else +// kernelStats->mode(Kernel::kernel); case ISA::IPR_ICM: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; + // only write two mode bits - processor mode + ipr[idx] = val & 0x18; + break; case ISA::IPR_ALT_MODE: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; + // only write two mode bits - processor mode + ipr[idx] = val & 0x18; + break; case ISA::IPR_MCSR: - // more here after optimization... - ipr[idx] = val; - break; + // more here after optimization... + ipr[idx] = val; + break; case ISA::IPR_SIRR: - // only write software interrupt mask - ipr[idx] = val & 0x7fff0; - break; + // only write software interrupt mask + ipr[idx] = val & 0x7fff0; + break; case ISA::IPR_ICSR: - ipr[idx] = val & ULL(0xffffff0300); - break; + ipr[idx] = val & ULL(0xffffff0300); + break; case ISA::IPR_IVPTBR: case ISA::IPR_MVPTBR: - ipr[idx] = val & ULL(0xffffffffc0000000); - break; + ipr[idx] = val & ULL(0xffffffffc0000000); + break; case ISA::IPR_DC_TEST_CTL: - ipr[idx] = val & 0x1ffb; - break; + ipr[idx] = val & 0x1ffb; + break; case ISA::IPR_DC_MODE: case ISA::IPR_MAF_MODE: - ipr[idx] = val & 0x3f; - break; + ipr[idx] = val & 0x3f; + break; case ISA::IPR_ITB_ASN: - ipr[idx] = val & 0x7f0; - break; + ipr[idx] = val & 0x7f0; + break; case ISA::IPR_DTB_ASN: - ipr[idx] = val & ULL(0xfe00000000000000); - break; + ipr[idx] = val & ULL(0xfe00000000000000); + break; case ISA::IPR_EXC_SUM: case ISA::IPR_EXC_MASK: - // any write to this register clears it - ipr[idx] = 0; - break; + // any write to this register clears it + ipr[idx] = 0; + break; case ISA::IPR_INTID: case ISA::IPR_SL_RCV: case ISA::IPR_MM_STAT: case ISA::IPR_ITB_PTE_TEMP: case ISA::IPR_DTB_PTE_TEMP: - // read-only registers - return Unimplemented_Opcode_Fault; + // read-only registers + return Unimplemented_Opcode_Fault; case ISA::IPR_HWINT_CLR: case ISA::IPR_SL_XMIT: case ISA::IPR_DC_FLUSH: case ISA::IPR_IC_FLUSH: - // the following are write only - ipr[idx] = val; - break; + // the following are write only + ipr[idx] = val; + break; case ISA::IPR_DTB_IA: - // really a control write - ipr[idx] = 0; + // really a control write + ipr[idx] = 0; - dtb->flushAll(); - break; + cpu->dtb->flushAll(); + break; case ISA::IPR_DTB_IAP: - // really a control write - ipr[idx] = 0; + // really a control write + ipr[idx] = 0; - dtb->flushProcesses(); - break; + cpu->dtb->flushProcesses(); + break; case ISA::IPR_DTB_IS: - // really a control write - ipr[idx] = val; + // really a control write + ipr[idx] = val; - dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN])); - break; + cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN])); + break; case ISA::IPR_DTB_TAG: { - struct ISA::PTE pte; - - // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]); - pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]); - pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]); - pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]); - pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]); - pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]); - pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]); - - // insert new TAG/PTE value into data TLB - dtb->insert(val, pte); + struct ISA::PTE pte; + + // FIXME: granularity hints NYI... + if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0) + panic("PTE GH field != 0"); + + // write entire quad + ipr[idx] = val; + + // construct PTE for new entry + pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]); + pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]); + pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]); + pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]); + pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]); + pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]); + pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]); + + // insert new TAG/PTE value into data TLB + cpu->dtb->insert(val, pte); } - break; + break; case ISA::IPR_ITB_PTE: { - struct ISA::PTE pte; - - // FIXME: granularity hints NYI... - if (ITB_PTE_GH(val) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - pte.ppn = ITB_PTE_PPN(val); - pte.xre = ITB_PTE_XRE(val); - pte.xwe = 0; - pte.fonr = ITB_PTE_FONR(val); - pte.fonw = ITB_PTE_FONW(val); - pte.asma = ITB_PTE_ASMA(val); - pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]); - - // insert new TAG/PTE value into data TLB - itb->insert(ipr[ISA::IPR_ITB_TAG], pte); + struct ISA::PTE pte; + + // FIXME: granularity hints NYI... + if (ITB_PTE_GH(val) != 0) + panic("PTE GH field != 0"); + + // write entire quad + ipr[idx] = val; + + // construct PTE for new entry + pte.ppn = ITB_PTE_PPN(val); + pte.xre = ITB_PTE_XRE(val); + pte.xwe = 0; + pte.fonr = ITB_PTE_FONR(val); + pte.fonw = ITB_PTE_FONW(val); + pte.asma = ITB_PTE_ASMA(val); + pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]); + + // insert new TAG/PTE value into data TLB + cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte); } - break; + break; case ISA::IPR_ITB_IA: - // really a control write - ipr[idx] = 0; + // really a control write + ipr[idx] = 0; - itb->flushAll(); - break; + cpu->itb->flushAll(); + break; case ISA::IPR_ITB_IAP: - // really a control write - ipr[idx] = 0; + // really a control write + ipr[idx] = 0; - itb->flushProcesses(); - break; + cpu->itb->flushProcesses(); + break; case ISA::IPR_ITB_IS: - // really a control write - ipr[idx] = val; + // really a control write + ipr[idx] = val; - itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN])); - break; + cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN])); + break; default: - // invalid IPR - return Unimplemented_Opcode_Fault; + // invalid IPR + return Unimplemented_Opcode_Fault; } // no error... @@ -596,4 +613,4 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val) #endif // #ifdef FULL_SYSTEM -#endif // __REGFILE_HH__ +#endif // __CPU_BETA_CPU_REGFILE_HH__ |