diff options
Diffstat (limited to 'cpu/cpu_exec_context.hh')
| -rw-r--r-- | cpu/cpu_exec_context.hh | 125 |
1 files changed, 61 insertions, 64 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index beaf67352..236619752 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -32,16 +32,13 @@ #include "arch/isa_traits.hh" #include "config/full_system.hh" #include "cpu/exec_context.hh" -#include "mem/functional/functional.hh" -#include "mem/mem_req.hh" +#include "mem/physical.hh" +#include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" #include "sim/host.hh" #include "sim/serialize.hh" -// forward declaration: see functional_memory.hh -class FunctionalMemory; -class PhysicalMemory; class BaseCPU; #if FULL_SYSTEM @@ -56,6 +53,8 @@ class MemoryController; #else // !FULL_SYSTEM #include "sim/process.hh" +#include "mem/page_table.hh" +class TranslatingPort; #endif // FULL_SYSTEM @@ -72,6 +71,8 @@ class CPUExecContext typedef TheISA::MachInst MachInst; typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; + typedef TheISA::FloatReg FloatReg; + typedef TheISA::FloatRegBits FloatRegBits; public: typedef ExecContext::Status Status; @@ -118,17 +119,21 @@ class CPUExecContext Tick lastActivate; Tick lastSuspend; + System *system; + + /// Port that syscalls can use to access memory (provides translation step). + TranslatingPort *port; +// Memory *mem; + #if FULL_SYSTEM - FunctionalMemory *mem; AlphaITB *itb; AlphaDTB *dtb; - System *system; // the following two fields are redundant, since we can always // look them up through the system pointer, but we'll leave them // here for now for convenience MemoryController *memctrl; - PhysicalMemory *physmem; +// PhysicalMemory *physmem; FunctionProfile *profile; ProfileNode *profileNode; @@ -164,8 +169,6 @@ class CPUExecContext #else Process *process; - FunctionalMemory *mem; // functional storage for process address space - // Address space ID. Note that this is used for TIMING cache // simulation only; all functional memory accesses should use // one of the FunctionalMemory pointers above. @@ -202,9 +205,7 @@ class CPUExecContext CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system, AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); #else - CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); - CPUExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, - int _asid); + CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port); // Constructor to use XC to pass reg file around. Not used for anything // else. CPUExecContext(RegFile *regFile); @@ -218,6 +219,8 @@ class CPUExecContext void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + TranslatingPort *getMemPort() { return port; } + BaseCPU *getCpuPtr() { return cpu; } ExecContext *getProxy() { return proxy; } @@ -233,22 +236,20 @@ class CPUExecContext AlphaDTB *getDTBPtr() { return dtb; } - bool validInstAddr(Addr addr) { return true; } - bool validDataAddr(Addr addr) { return true; } int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault translateInstReq(MemReqPtr &req) + Fault translateInstReq(CpuRequestPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(CpuRequestPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(CpuRequestPtr &req) { return dtb->translate(req, true); } @@ -256,45 +257,31 @@ class CPUExecContext #else Process *getProcessPtr() { return process; } - bool validInstAddr(Addr addr) - { return process->validInstAddr(addr); } - - bool validDataAddr(Addr addr) - { return process->validDataAddr(addr); } - int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault dummyTranslation(MemReqPtr &req) - { -#if 0 - assert((req->vaddr >> 48 & 0xffff) == 0); -#endif - - // put the asid in the upper 16 bits of the paddr - req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); - req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return NoFault; - } - Fault translateInstReq(MemReqPtr &req) + Fault translateInstReq(CpuRequestPtr &req) { - return dummyTranslation(req); + return process->pTable->translate(req); } - Fault translateDataReadReq(MemReqPtr &req) + + Fault translateDataReadReq(CpuRequestPtr &req) { - return dummyTranslation(req); + return process->pTable->translate(req); } - Fault translateDataWriteReq(MemReqPtr &req) + + Fault translateDataWriteReq(CpuRequestPtr &req) { - return dummyTranslation(req); + return process->pTable->translate(req); } #endif +/* template <class T> - Fault read(MemReqPtr &req, T &data) + Fault read(CpuRequestPtr &req, T &data) { -#if FULL_SYSTEM && defined(TARGET_ALPHA) +#if FULL_SYSTEM && THE_ISA == ALPHA_ISA if (req->flags & LOCKED) { req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); @@ -302,15 +289,15 @@ class CPUExecContext #endif Fault error; - error = mem->read(req, data); + error = mem->prot_read(req->paddr, data, req->size); data = LittleEndianGuest::gtoh(data); return error; } template <class T> - Fault write(MemReqPtr &req, T &data) + Fault write(CpuRequestPtr &req, T &data) { -#if FULL_SYSTEM && defined(TARGET_ALPHA) +#if FULL_SYSTEM && THE_ISA == ALPHA_ISA ExecContext *xc; // If this is a store conditional, act appropriately @@ -356,9 +343,9 @@ class CPUExecContext } #endif - return mem->write(req, (T)LittleEndianGuest::htog(data)); + return mem->prot_write(req->paddr, (T)htog(data), req->size); } - +*/ virtual bool misspeculating(); @@ -369,17 +356,17 @@ class CPUExecContext inst = new_inst; } - Fault instRead(MemReqPtr &req) + Fault instRead(CpuRequestPtr &req) { - return mem->read(req, inst); + panic("instRead not implemented"); + // return funcPhysMem->read(req, inst); + return NoFault; } void setCpuId(int id) { cpu_id = id; } int readCpuId() { return cpu_id; } - FunctionalMemory *getMemPtr() { return mem; } - void copyArchRegs(ExecContext *xc); // @@ -390,19 +377,24 @@ class CPUExecContext return regs.intRegFile[reg_idx]; } - float readFloatRegSingle(int reg_idx) + FloatReg readFloatReg(int reg_idx, int width) { - return (float)regs.floatRegFile.d[reg_idx]; + return regs.floatRegFile.readReg(reg_idx, width); } - double readFloatRegDouble(int reg_idx) + FloatReg readFloatReg(int reg_idx) { - return regs.floatRegFile.d[reg_idx]; + return regs.floatRegFile.readReg(reg_idx); } - uint64_t readFloatRegInt(int reg_idx) + FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.floatRegFile.q[reg_idx]; + return regs.floatRegFile.readRegBits(reg_idx, width); + } + + FloatRegBits readFloatRegBits(int reg_idx) + { + return regs.floatRegFile.readRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) @@ -410,19 +402,24 @@ class CPUExecContext regs.intRegFile[reg_idx] = val; } - void setFloatRegSingle(int reg_idx, float val) + void setFloatReg(int reg_idx, FloatReg val, int width) + { + regs.floatRegFile.setReg(reg_idx, val, width); + } + + void setFloatReg(int reg_idx, FloatReg val) { - regs.floatRegFile.d[reg_idx] = (double)val; + regs.floatRegFile.setReg(reg_idx, val); } - void setFloatRegDouble(int reg_idx, double val) + void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.floatRegFile.d[reg_idx] = val; + regs.floatRegFile.setRegBits(reg_idx, val, width); } - void setFloatRegInt(int reg_idx, uint64_t val) + void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.floatRegFile.q[reg_idx] = val; + regs.floatRegFile.setRegBits(reg_idx, val); } uint64_t readPC() |