diff options
Diffstat (limited to 'cpu/cpu_exec_context.hh')
| -rw-r--r-- | cpu/cpu_exec_context.hh | 121 |
1 files changed, 70 insertions, 51 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 236619752..eb5d712b9 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -48,7 +48,9 @@ class BaseCPU; class FunctionProfile; class ProfileNode; -class MemoryController; +class FunctionalPort; +class PhysicalPort; + #else // !FULL_SYSTEM @@ -56,6 +58,7 @@ class MemoryController; #include "mem/page_table.hh" class TranslatingPort; + #endif // FULL_SYSTEM // @@ -121,19 +124,18 @@ class CPUExecContext System *system; - /// Port that syscalls can use to access memory (provides translation step). - TranslatingPort *port; -// Memory *mem; #if FULL_SYSTEM AlphaITB *itb; AlphaDTB *dtb; - // the following two fields are redundant, since we can always - // look them up through the system pointer, but we'll leave them - // here for now for convenience - MemoryController *memctrl; -// PhysicalMemory *physmem; + /** A functional port outgoing only for functional accesses to physical + * addresses.*/ + FunctionalPort *physPort; + + /** A functional port, outgoing only, for functional accesse to virtual + * addresses. That doen't require execution context information */ + VirtualPort *virtPort; FunctionProfile *profile; ProfileNode *profileNode; @@ -167,6 +169,9 @@ class CPUExecContext void profileSample(); #else + /// Port that syscalls can use to access memory (provides translation step). + TranslatingPort *port; + Process *process; // Address space ID. Note that this is used for TIMING cache @@ -203,9 +208,10 @@ class CPUExecContext // constructor: initialize context from given process structure #if FULL_SYSTEM CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system, - AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); + AlphaITB *_itb, AlphaDTB *_dtb); #else - CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port); + CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, + MemObject *memobj); // Constructor to use XC to pass reg file around. Not used for anything // else. CPUExecContext(RegFile *regFile); @@ -219,8 +225,6 @@ class CPUExecContext void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); - TranslatingPort *getMemPort() { return port; } - BaseCPU *getCpuPtr() { return cpu; } ExecContext *getProxy() { return proxy; } @@ -230,8 +234,6 @@ class CPUExecContext #if FULL_SYSTEM System *getSystemPtr() { return system; } - PhysicalMemory *getPhysMemPtr() { return physmem; } - AlphaITB *getITBPtr() { return itb; } AlphaDTB *getDTBPtr() { return dtb; } @@ -239,38 +241,49 @@ class CPUExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault translateInstReq(CpuRequestPtr &req) + Fault translateInstReq(RequestPtr &req) { - return itb->translate(req); + return itb->translate(req, proxy); } - Fault translateDataReadReq(CpuRequestPtr &req) + Fault translateDataReadReq(RequestPtr &req) { - return dtb->translate(req, false); + return dtb->translate(req, proxy, false); } - Fault translateDataWriteReq(CpuRequestPtr &req) + Fault translateDataWriteReq(RequestPtr &req) { - return dtb->translate(req, true); + return dtb->translate(req, proxy, true); } + FunctionalPort *getPhysPort() { return physPort; } + + /** Return a virtual port. If no exec context is specified then a static + * port is returned. Otherwise a port is created and returned. It must be + * deleted by deleteVirtPort(). */ + VirtualPort *getVirtPort(ExecContext *xc); + + void delVirtPort(VirtualPort *vp); + #else + TranslatingPort *getMemPort() { return port; } + Process *getProcessPtr() { return process; } int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault translateInstReq(CpuRequestPtr &req) + Fault translateInstReq(RequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataReadReq(CpuRequestPtr &req) + Fault translateDataReadReq(RequestPtr &req) { return process->pTable->translate(req); } - Fault translateDataWriteReq(CpuRequestPtr &req) + Fault translateDataWriteReq(RequestPtr &req) { return process->pTable->translate(req); } @@ -279,7 +292,7 @@ class CPUExecContext /* template <class T> - Fault read(CpuRequestPtr &req, T &data) + Fault read(RequestPtr &req, T &data) { #if FULL_SYSTEM && THE_ISA == ALPHA_ISA if (req->flags & LOCKED) { @@ -295,7 +308,7 @@ class CPUExecContext } template <class T> - Fault write(CpuRequestPtr &req, T &data) + Fault write(RequestPtr &req, T &data) { #if FULL_SYSTEM && THE_ISA == ALPHA_ISA ExecContext *xc; @@ -356,7 +369,7 @@ class CPUExecContext inst = new_inst; } - Fault instRead(CpuRequestPtr &req) + Fault instRead(RequestPtr &req) { panic("instRead not implemented"); // return funcPhysMem->read(req, inst); @@ -374,103 +387,103 @@ class CPUExecContext // uint64_t readIntReg(int reg_idx) { - return regs.intRegFile[reg_idx]; + return regs.readIntReg(reg_idx); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.floatRegFile.readReg(reg_idx, width); + return regs.readFloatReg(reg_idx, width); } FloatReg readFloatReg(int reg_idx) { - return regs.floatRegFile.readReg(reg_idx); + return regs.readFloatReg(reg_idx); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.floatRegFile.readRegBits(reg_idx, width); + return regs.readFloatRegBits(reg_idx, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.floatRegFile.readRegBits(reg_idx); + return regs.readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { - regs.intRegFile[reg_idx] = val; + regs.setIntReg(reg_idx, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.floatRegFile.setReg(reg_idx, val, width); + regs.setFloatReg(reg_idx, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.floatRegFile.setReg(reg_idx, val); + regs.setFloatReg(reg_idx, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.floatRegFile.setRegBits(reg_idx, val, width); + regs.setFloatRegBits(reg_idx, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.floatRegFile.setRegBits(reg_idx, val); + regs.setFloatRegBits(reg_idx, val); } uint64_t readPC() { - return regs.pc; + return regs.readPC(); } void setPC(uint64_t val) { - regs.pc = val; + regs.setPC(val); } uint64_t readNextPC() { - return regs.npc; + return regs.readNextPC(); } void setNextPC(uint64_t val) { - regs.npc = val; + regs.setNextPC(val); } uint64_t readNextNPC() { - return regs.nnpc; + return regs.readNextNPC(); } void setNextNPC(uint64_t val) { - regs.nnpc = val; + regs.setNextNPC(val); } MiscReg readMiscReg(int misc_reg) { - return regs.miscRegs.readReg(misc_reg); + return regs.readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy); + return regs.readMiscRegWithEffect(misc_reg, fault, proxy); } Fault setMiscReg(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setReg(misc_reg, val); + return regs.setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy); + return regs.setMiscRegWithEffect(misc_reg, val, proxy); } unsigned readStCondFailures() { return storeCondFailures; } @@ -478,26 +491,26 @@ class CPUExecContext void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } - void clearArchRegs() { memset(®s, 0, sizeof(regs)); } + void clearArchRegs() { regs.clear(); } #if FULL_SYSTEM int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); - bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } + bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); } bool simPalCheck(int palFunc); #endif #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { - return regs.intRegFile[TheISA::ArgumentReg0 + i]; + return regs.readIntReg(TheISA::ArgumentReg0 + i); } // used to shift args for indirect syscall void setSyscallArg(int i, TheISA::IntReg val) { - regs.intRegFile[TheISA::ArgumentReg0 + i] = val; + regs.setIntReg(TheISA::ArgumentReg0 + i, val); } void setSyscallReturn(SyscallReturn return_value) @@ -514,6 +527,12 @@ class CPUExecContext void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; } #endif + + void changeRegFileContext(RegFile::ContextParam param, + RegFile::ContextVal val) + { + regs.changeContext(param, val); + } }; |