1 files changed, 43 insertions, 21 deletions

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 3e0d77254..d8ec88537 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
+ * Copyright (c) 2001-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,7 @@
 #include "config/full_system.hh"
 #include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
+#include "sim/eventq.hh"
 #include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "arch/isa_traits.hh"
@@ -46,7 +47,7 @@ class BaseCPU;
 #if FULL_SYSTEM
 
 #include "sim/system.hh"
-#include "targetarch/alpha_memory.hh"
+#include "arch/tlb.hh"
 
 class FunctionProfile;
 class ProfileNode;
@@ -71,6 +72,7 @@ class ExecContext
     typedef TheISA::RegFile RegFile;
     typedef TheISA::MachInst MachInst;
     typedef TheISA::MiscRegFile MiscRegFile;
+    typedef TheISA::MiscReg MiscReg;
   public:
     enum Status
     {
@@ -131,6 +133,9 @@ class ExecContext
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpu_id;
 
+    Tick lastActivate;
+    Tick lastSuspend;
+
 #if FULL_SYSTEM
     FunctionalMemory *mem;
     AlphaITB *itb;
@@ -153,6 +158,22 @@ class ExecContext
     Addr profilePC;
     void dumpFuncProfile();
 
+    /** Event for timing out quiesce instruction */
+    struct EndQuiesceEvent : public Event
+    {
+        /** A pointer to the execution context that is quiesced */
+        ExecContext *xc;
+
+        EndQuiesceEvent(ExecContext *_xc);
+
+        /** Event process to occur at interrupt*/
+        virtual void process();
+
+        /** Event description */
+        virtual const char *description();
+    };
+    EndQuiesceEvent quiesceEvent;
+
 #else
     Process *process;
 
@@ -270,8 +291,8 @@ class ExecContext
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
-            cregs->lock_addr = req->paddr;
-            cregs->lock_flag = true;
+            cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
+            cregs->setReg(TheISA::Lock_Flag_DepTag, true);
         }
 #endif
 
@@ -297,10 +318,12 @@ class ExecContext
                 req->result = 2;
                 req->xc->storeCondFailures = 0;//Needed? [RGD]
             } else {
-                req->result = cregs->lock_flag;
-                if (!cregs->lock_flag ||
-                    ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
-                    cregs->lock_flag = false;
+                bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
+                Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
+                req->result = lock_flag;
+                if (!lock_flag ||
+                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+                    cregs->setReg(TheISA::Lock_Flag_DepTag, false);
                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
                         std::cerr << "Warning: "
                                   << req->xc->storeCondFailures
@@ -321,8 +344,9 @@ class ExecContext
         // through.
         for (int i = 0; i < system->execContexts.size(); i++){
             cregs = &system->execContexts[i]->regs.miscRegs;
-            if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
-                cregs->lock_flag = false;
+            if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+                (req->paddr & ~0xf)) {
+                cregs->setReg(TheISA::Lock_Flag_DepTag, false);
             }
         }
 
@@ -398,34 +422,32 @@ class ExecContext
         regs.npc = val;
     }
 
-    uint64_t readUniq()
+    MiscReg readMiscReg(int misc_reg)
     {
-        return regs.miscRegs.uniq;
+        return regs.miscRegs.readReg(misc_reg);
     }
 
-    void setUniq(uint64_t val)
+    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        regs.miscRegs.uniq = val;
+        return regs.miscRegs.readRegWithEffect(misc_reg, fault, this);
     }
 
-    uint64_t readFpcr()
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return regs.miscRegs.fpcr;
+        return regs.miscRegs.setReg(misc_reg, val);
     }
 
-    void setFpcr(uint64_t val)
+    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        regs.miscRegs.fpcr = val;
+        return regs.miscRegs.setRegWithEffect(misc_reg, val, this);
     }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
     void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
-    void ev5_trap(Fault fault);
+    void ev5_temp_trap(Fault fault);
     bool simPalCheck(int palFunc);
 #endif