1 files changed, 16 insertions, 16 deletions

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 3fa7d078e..3e0d77254 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -213,17 +213,17 @@ class ExecContext
     int getInstAsid() { return regs.instAsid(); }
     int getDataAsid() { return regs.dataAsid(); }
 
-    Fault * translateInstReq(MemReqPtr &req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault * translateDataReadReq(MemReqPtr &req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault * translateDataWriteReq(MemReqPtr &req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
@@ -238,7 +238,7 @@ class ExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault * dummyTranslation(MemReqPtr &req)
+    Fault dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -249,15 +249,15 @@ class ExecContext
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
         return NoFault;
     }
-    Fault * translateInstReq(MemReqPtr &req)
+    Fault translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault * translateDataReadReq(MemReqPtr &req)
+    Fault translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault * translateDataWriteReq(MemReqPtr &req)
+    Fault translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -265,7 +265,7 @@ class ExecContext
 #endif
 
     template <class T>
-    Fault * read(MemReqPtr &req, T &data)
+    Fault read(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
@@ -275,14 +275,14 @@ class ExecContext
         }
 #endif
 
-        Fault * error;
+        Fault error;
         error = mem->read(req, data);
         data = LittleEndianGuest::gtoh(data);
         return error;
     }
 
     template <class T>
-    Fault * write(MemReqPtr &req, T &data)
+    Fault write(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 
@@ -340,7 +340,7 @@ class ExecContext
         inst = new_inst;
     }
 
-    Fault * instRead(MemReqPtr &req)
+    Fault instRead(MemReqPtr &req)
     {
         return mem->read(req, inst);
     }
@@ -419,13 +419,13 @@ class ExecContext
     }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault * &fault);
-    Fault * setIpr(int idx, uint64_t val);
+    uint64_t readIpr(int idx, Fault &fault);
+    Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
     void setIntrFlag(int val) { regs.intrflag = val; }
-    Fault * hwrei();
+    Fault hwrei();
     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
-    void ev5_trap(Fault * fault);
+    void ev5_trap(Fault fault);
     bool simPalCheck(int palFunc);
 #endif
 
@@ -435,7 +435,7 @@ class ExecContext
      *  @todo How to do this properly so it's dependent upon ISA only?
      */
 
-    void trap(Fault * fault);
+    void trap(Fault fault);
 
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)