diff options
Diffstat (limited to 'cpu/o3/cpu_policy.hh')
| -rw-r--r-- | cpu/o3/cpu_policy.hh | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/cpu/o3/cpu_policy.hh b/cpu/o3/cpu_policy.hh index b4249b12d..c30e58389 100644 --- a/cpu/o3/cpu_policy.hh +++ b/cpu/o3/cpu_policy.hh @@ -48,24 +48,50 @@ #include "cpu/o3/comm.hh" +/** + * Struct that defines the key classes to be used by the CPU. All + * classes use the typedefs defined here to determine what are the + * classes of the other stages and communication buffers. In order to + * change a structure such as the IQ, simply change the typedef here + * to use the desired class instead, and recompile. In order to + * create a different CPU to be used simultaneously with this one, see + * the alpha_impl.hh file for instructions. + */ template<class Impl> struct SimpleCPUPolicy { + /** Typedef for the branch prediction unit (which includes the BP, + * RAS, and BTB). + */ typedef BPredUnit<Impl> BPredUnit; + /** Typedef for the register file. Most classes assume a unified + * physical register file. + */ typedef PhysRegFile<Impl> RegFile; + /** Typedef for the freelist of registers. */ typedef SimpleFreeList FreeList; + /** Typedef for the rename map. */ typedef SimpleRenameMap RenameMap; + /** Typedef for the ROB. */ typedef ROB<Impl> ROB; + /** Typedef for the instruction queue/scheduler. */ typedef InstructionQueue<Impl> IQ; + /** Typedef for the memory dependence unit. */ typedef MemDepUnit<StoreSet, Impl> MemDepUnit; + /** Typedef for the LSQ. */ typedef LSQ<Impl> LSQ; + /** Typedef for the thread-specific LSQ units. */ typedef LSQUnit<Impl> LSQUnit; - + /** Typedef for fetch. */ typedef DefaultFetch<Impl> Fetch; + /** Typedef for decode. */ typedef DefaultDecode<Impl> Decode; + /** Typedef for rename. */ typedef DefaultRename<Impl> Rename; + /** Typedef for Issue/Execute/Writeback. */ typedef DefaultIEW<Impl> IEW; + /** Typedef for commit. */ typedef DefaultCommit<Impl> Commit; /** The struct for communication between fetch and decode. */ |