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-rw-r--r--cpu/o3/regfile.hh404
1 files changed, 17 insertions, 387 deletions
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 4d47b8f9c..1e6e10f29 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -31,16 +31,15 @@
// @todo: Destructor
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "arch/alpha/ev5.hh"
#include "kern/kernel_stats.hh"
-using namespace EV5;
#endif
// This really only depends on the ISA, and not the Impl. It might be nicer
@@ -51,6 +50,12 @@ using namespace EV5;
template <class Impl>
class PhysRegFile
{
+ protected:
+ typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::MiscRegFile MiscRegFile;
+ typedef TheISA::MiscReg MiscReg;
+
//Note that most of the definitions of the IntReg, FloatReg, etc. exist
//within the Impl/ISA class and not within this PhysRegFile class.
@@ -61,7 +66,6 @@ class PhysRegFile
//Will make these registers public for now, but they probably should
//be private eventually with some accessor functions.
public:
- typedef typename Impl::ISA ISA;
typedef typename Impl::FullCPU FullCPU;
PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -190,30 +194,21 @@ class PhysRegFile
//Consider leaving this stuff and below in some implementation specific
//file as opposed to the general register file. Or have a derived class.
- uint64_t readUniq()
- {
- return miscRegs.uniq;
- }
-
- void setUniq(uint64_t val)
- {
- miscRegs.uniq = val;
- }
-
- uint64_t readFpcr()
+ MiscReg readMiscReg(int misc_reg)
{
- return miscRegs.fpcr;
+ // Dummy function for now.
+ // @todo: Fix this once proxy XC is used.
+ return 0;
}
- void setFpcr(uint64_t val)
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- miscRegs.fpcr = val;
+ // Dummy function for now.
+ // @todo: Fix this once proxy XC is used.
+ return NoFault;
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
- InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
#endif
@@ -239,8 +234,7 @@ class PhysRegFile
#if FULL_SYSTEM
private:
// This is ISA specifc stuff; remove it eventually once ISAImpl is used
- IntReg palregs[NumIntRegs]; // PAL shadow registers
- InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
+// IntReg palregs[NumIntRegs]; // PAL shadow registers
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
#endif
@@ -268,368 +262,4 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
memset(floatRegFile, 0, sizeof(*floatRegFile));
}
-#if FULL_SYSTEM
-
-//Problem: This code doesn't make sense at the RegFile level because it
-//needs things such as the itb and dtb. Either put it at the CPU level or
-//the DynInst level.
-template <class Impl>
-uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
-{
- uint64_t retval = 0; // return value, default 0
-
- switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PALtemp23:
- case ISA::IPR_PAL_BASE:
-
- case ISA::IPR_IVPTBR:
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
- case ISA::IPR_ISR:
- case ISA::IPR_EXC_ADDR:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_MCSR:
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
- case ISA::IPR_SIRR:
- case ISA::IPR_ICSR:
- case ISA::IPR_ICM:
- case ISA::IPR_DTB_CM:
- case ISA::IPR_IPLR:
- case ISA::IPR_INTID:
- case ISA::IPR_PMCTR:
- // no side-effect
- retval = ipr[idx];
- break;
-
- case ISA::IPR_CC:
- retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= curTick & ULL(0x00000000ffffffff);
- break;
-
- case ISA::IPR_VA:
- retval = ipr[idx];
- break;
-
- case ISA::IPR_VA_FORM:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_IFAULT_VA_FORM:
- case ISA::IPR_EXC_MASK:
- case ISA::IPR_EXC_SUM:
- retval = ipr[idx];
- break;
-
- case ISA::IPR_DTB_PTE:
- {
- typename ISA::PTE &pte = cpu->dtb->index(1);
-
- retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
- retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
- retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
- retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
- retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
- retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
- retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
- }
- break;
-
- // write only registers
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
- case ISA::IPR_ALT_MODE:
- case ISA::IPR_DTB_IA:
- case ISA::IPR_DTB_IAP:
- case ISA::IPR_ITB_IA:
- case ISA::IPR_ITB_IAP:
- fault = Unimplemented_Opcode_Fault;
- break;
-
- default:
- // invalid IPR
- fault = Unimplemented_Opcode_Fault;
- break;
- }
-
- return retval;
-}
-
-extern int break_ipl;
-
-template <class Impl>
-Fault
-PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
-{
- uint64_t old;
-
- switch (idx) {
- case ISA::IPR_PALtemp0:
- case ISA::IPR_PALtemp1:
- case ISA::IPR_PALtemp2:
- case ISA::IPR_PALtemp3:
- case ISA::IPR_PALtemp4:
- case ISA::IPR_PALtemp5:
- case ISA::IPR_PALtemp6:
- case ISA::IPR_PALtemp7:
- case ISA::IPR_PALtemp8:
- case ISA::IPR_PALtemp9:
- case ISA::IPR_PALtemp10:
- case ISA::IPR_PALtemp11:
- case ISA::IPR_PALtemp12:
- case ISA::IPR_PALtemp13:
- case ISA::IPR_PALtemp14:
- case ISA::IPR_PALtemp15:
- case ISA::IPR_PALtemp16:
- case ISA::IPR_PALtemp17:
- case ISA::IPR_PALtemp18:
- case ISA::IPR_PALtemp19:
- case ISA::IPR_PALtemp20:
- case ISA::IPR_PALtemp21:
- case ISA::IPR_PALtemp22:
- case ISA::IPR_PAL_BASE:
- case ISA::IPR_IC_PERR_STAT:
- case ISA::IPR_DC_PERR_STAT:
- case ISA::IPR_PMCTR:
- // write entire quad w/ no side-effect
- ipr[idx] = val;
- break;
-
- case ISA::IPR_CC_CTL:
- // This IPR resets the cycle counter. We assume this only
- // happens once... let's verify that.
- assert(ipr[idx] == 0);
- ipr[idx] = 1;
- break;
-
- case ISA::IPR_CC:
- // This IPR only writes the upper 64 bits. It's ok to write
- // all 64 here since we mask out the lower 32 in rpcc (see
- // isa_desc).
- ipr[idx] = val;
- break;
-
- case ISA::IPR_PALtemp23:
- // write entire quad w/ no side-effect
- old = ipr[idx];
- ipr[idx] = val;
- break;
-
- case ISA::IPR_DTB_PTE:
- // write entire quad w/ no side-effect, tag is forthcoming
- ipr[idx] = val;
- break;
-
- case ISA::IPR_EXC_ADDR:
- // second least significant bit in PC is always zero
- ipr[idx] = val & ~2;
- break;
-
- case ISA::IPR_ASTRR:
- case ISA::IPR_ASTER:
- // only write least significant four bits - privilege mask
- ipr[idx] = val & 0xf;
- break;
-
- case ISA::IPR_IPLR:
- // only write least significant five bits - interrupt level
- ipr[idx] = val & 0x1f;
- break;
-
- case ISA::IPR_DTB_CM:
-
- case ISA::IPR_ICM:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case ISA::IPR_ALT_MODE:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case ISA::IPR_MCSR:
- // more here after optimization...
- ipr[idx] = val;
- break;
-
- case ISA::IPR_SIRR:
- // only write software interrupt mask
- ipr[idx] = val & 0x7fff0;
- break;
-
- case ISA::IPR_ICSR:
- ipr[idx] = val & ULL(0xffffff0300);
- break;
-
- case ISA::IPR_IVPTBR:
- case ISA::IPR_MVPTBR:
- ipr[idx] = val & ULL(0xffffffffc0000000);
- break;
-
- case ISA::IPR_DC_TEST_CTL:
- ipr[idx] = val & 0x1ffb;
- break;
-
- case ISA::IPR_DC_MODE:
- case ISA::IPR_MAF_MODE:
- ipr[idx] = val & 0x3f;
- break;
-
- case ISA::IPR_ITB_ASN:
- ipr[idx] = val & 0x7f0;
- break;
-
- case ISA::IPR_DTB_ASN:
- ipr[idx] = val & ULL(0xfe00000000000000);
- break;
-
- case ISA::IPR_EXC_SUM:
- case ISA::IPR_EXC_MASK:
- // any write to this register clears it
- ipr[idx] = 0;
- break;
-
- case ISA::IPR_INTID:
- case ISA::IPR_SL_RCV:
- case ISA::IPR_MM_STAT:
- case ISA::IPR_ITB_PTE_TEMP:
- case ISA::IPR_DTB_PTE_TEMP:
- // read-only registers
- return Unimplemented_Opcode_Fault;
-
- case ISA::IPR_HWINT_CLR:
- case ISA::IPR_SL_XMIT:
- case ISA::IPR_DC_FLUSH:
- case ISA::IPR_IC_FLUSH:
- // the following are write only
- ipr[idx] = val;
- break;
-
- case ISA::IPR_DTB_IA:
- // really a control write
- ipr[idx] = 0;
-
- cpu->dtb->flushAll();
- break;
-
- case ISA::IPR_DTB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- cpu->dtb->flushProcesses();
- break;
-
- case ISA::IPR_DTB_IS:
- // really a control write
- ipr[idx] = val;
-
- cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
- break;
-
- case ISA::IPR_DTB_TAG: {
- struct ISA::PTE pte;
-
- // FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
- pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
- pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
- pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
- pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
- pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
- pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- cpu->dtb->insert(val, pte);
- }
- break;
-
- case ISA::IPR_ITB_PTE: {
- struct ISA::PTE pte;
-
- // FIXME: granularity hints NYI...
- if (ITB_PTE_GH(val) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- pte.ppn = ITB_PTE_PPN(val);
- pte.xre = ITB_PTE_XRE(val);
- pte.xwe = 0;
- pte.fonr = ITB_PTE_FONR(val);
- pte.fonw = ITB_PTE_FONW(val);
- pte.asma = ITB_PTE_ASMA(val);
- pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
- }
- break;
-
- case ISA::IPR_ITB_IA:
- // really a control write
- ipr[idx] = 0;
-
- cpu->itb->flushAll();
- break;
-
- case ISA::IPR_ITB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- cpu->itb->flushProcesses();
- break;
-
- case ISA::IPR_ITB_IS:
- // really a control write
- ipr[idx] = val;
-
- cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
- break;
-
- default:
- // invalid IPR
- return Unimplemented_Opcode_Fault;
- }
-
- // no error...
- return No_Fault;
-}
-
-#endif // #if FULL_SYSTEM
-
#endif // __CPU_O3_CPU_REGFILE_HH__
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