summaryrefslogtreecommitdiff
path: root/cpu/o3
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/o3')
-rw-r--r--cpu/o3/alpha_cpu.hh38
-rw-r--r--cpu/o3/alpha_cpu_impl.hh26
-rw-r--r--cpu/o3/alpha_dyn_inst.hh14
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh8
-rw-r--r--cpu/o3/commit_impl.hh4
-rw-r--r--cpu/o3/fetch.hh2
-rw-r--r--cpu/o3/fetch_impl.hh14
-rw-r--r--cpu/o3/regfile.hh19
8 files changed, 63 insertions, 62 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 1e1a72af0..606f9fa0a 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -62,23 +62,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// void clear_interrupt(int int_num, int index);
// void clear_interrupts();
- Fault translateInstReq(MemReqPtr &req)
+ Fault * translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault * translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault * translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
#else
- Fault dummyTranslation(MemReqPtr &req)
+ Fault * dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -87,20 +87,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
- return No_Fault;
+ return NoFault;
}
- Fault translateInstReq(MemReqPtr &req)
+ Fault * translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault * translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault * translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -135,16 +135,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault * &fault);
+ Fault * setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
- Fault hwrei();
+ Fault * hwrei();
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
- void trap(Fault fault);
+ void trap(Fault * fault);
bool simPalCheck(int palFunc);
void processInterrupts();
@@ -197,7 +197,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
bool palShadowEnabled;
// Not sure this is used anywhere.
- void intr_post(RegFile *regs, Fault fault, Addr pc);
+ void intr_post(RegFile *regs, Fault * fault, Addr pc);
// Actually used within exec files. Implement properly.
void swapPALShadow(bool use_shadow);
// Called by CPU constructor. Can implement as I please.
@@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T>
- Fault read(MemReqPtr &req, T &data)
+ Fault * read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -220,20 +220,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
- Fault error;
+ Fault * error;
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
template <class T>
- Fault read(MemReqPtr &req, T &data, int load_idx)
+ Fault * read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
template <class T>
- Fault write(MemReqPtr &req, T &data)
+ Fault * write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -259,7 +259,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
<< "on cpu " << this->cpu_id
<< std::endl;
}
- return No_Fault;
+ return NoFault;
}
else req->xc->storeCondFailures = 0;
}
@@ -283,7 +283,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
template <class T>
- Fault write(MemReqPtr &req, T &data, int store_idx)
+ Fault * write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 3b16975a9..408676331 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
template <class Impl>
uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
+AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
-Fault
+Fault *
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
@@ -274,13 +274,13 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
// Can force commit stage to squash and stuff.
template <class Impl>
-Fault
+Fault *
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
if (!inPalMode())
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei()
this->checkInterrupts = true;
// FIXME: XXX check for interrupts? XXX
- return No_Fault;
+ return NoFault;
}
template <class Impl>
@@ -323,28 +323,28 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
// stage.
template <class Impl>
void
-AlphaFullCPU<Impl>::trap(Fault fault)
+AlphaFullCPU<Impl>::trap(Fault * fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", FaultName(fault));
- this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+ DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
+ this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
// kernelStats.fault(fault);
- if (fault == Arithmetic_Fault)
+ if (fault == ArithmeticFault)
panic("Arithmetic traps are unimplemented!");
typename AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
- if (fault != Interrupt_Fault || !inPalMode(PC))
+ if (fault != InterruptFault || !inPalMode(PC))
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
- if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
- fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+ if (fault == PalFault || fault == ArithmeticFault /* ||
+ fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
}
@@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
swapPALShadow(true);
this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
- AlphaISA::fault_addr[fault] );
+ AlphaISA::fault_addr(fault) );
this->regFile.setNextPC(PC + sizeof(MachInst));
}
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index bb90bf21a..77dcbaf74 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
/** Executes the instruction.*/
- Fault execute()
+ Fault * execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
@@ -87,13 +87,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFpcr(uint64_t val);
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
- Fault hwrei();
+ uint64_t readIpr(int idx, Fault * &fault);
+ Fault * setIpr(int idx, uint64_t val);
+ Fault * hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
- void trap(Fault fault);
+ void trap(Fault * fault);
bool simPalCheck(int palFunc);
#else
void syscall();
@@ -220,12 +220,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
- Fault calcEA()
+ Fault * calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
- Fault memAccess()
+ Fault * memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index d1ebb812d..b20af48cd 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
+AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
-Fault
+Fault *
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
-Fault
+Fault *
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
-AlphaDynInst<Impl>::trap(Fault fault)
+AlphaDynInst<Impl>::trap(Fault * fault)
{
this->cpu->trap(fault);
}
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index dc0986772..540f16b78 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -393,9 +393,9 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
// Check if the instruction caused a fault. If so, trap.
- Fault inst_fault = head_inst->getFault();
+ Fault * inst_fault = head_inst->getFault();
- if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
+ if (inst_fault != NoFault && inst_fault != FakeMemFault) {
if (!head_inst->isNop()) {
#if FULL_SYSTEM
cpu->trap(inst_fault);
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 24e445f0b..5443d274e 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -123,7 +123,7 @@ class SimpleFetch
* @param fetch_PC The PC address that is being fetched from.
* @return Any fault that occured.
*/
- Fault fetchCacheLine(Addr fetch_PC);
+ Fault * fetchCacheLine(Addr fetch_PC);
inline void doSquash(const Addr &new_PC);
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index cd1ed1351..e8d333ed4 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
-Fault
+Fault *
SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
{
// Check if the instruction exists within the cache.
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
- Fault fault = No_Fault;
+ Fault * fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// If translation was successful, attempt to read the first
// instruction.
- if (fault == No_Fault) {
+ if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
fault = cpu->mem->read(memReq, cacheData);
// This read may change when the mem interface changes.
@@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
// Now do the timing access to see whether or not the instruction
// exists within the cache.
- if (icacheInterface && fault == No_Fault) {
+ if (icacheInterface && fault == NoFault) {
DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
memReq->completionEvent = NULL;
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
- Fault fault = No_Fault;
+ Fault * fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
@@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch()
unsigned offset = fetch_PC & cacheBlkMask;
unsigned fetched;
- if (fault == No_Fault) {
+ if (fault == NoFault) {
// If the read of the first instruction was successful, then grab the
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
@@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch()
// Or might want to leave setting the PC to the main CPU, with fetch
// only changing the nextPC (will require correct determination of
// next PC).
- if (fault == No_Fault) {
+ if (fault == NoFault) {
DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
cpu->setPC(next_PC);
cpu->setNextPC(next_PC + instSize);
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 4d47b8f9c..5aafd5495 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -32,6 +32,7 @@
// @todo: Destructor
#include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/faults.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
@@ -211,8 +212,8 @@ class PhysRegFile
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault * &fault);
+ Fault * setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
@@ -275,7 +276,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
//the DynInst level.
template <class Impl>
uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
+PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
{
uint64_t retval = 0; // return value, default 0
@@ -368,12 +369,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
case ISA::IPR_DTB_IAP:
case ISA::IPR_ITB_IA:
case ISA::IPR_ITB_IAP:
- fault = Unimplemented_Opcode_Fault;
+ fault = UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = Unimplemented_Opcode_Fault;
+ fault = UnimplementedOpcodeFault;
break;
}
@@ -383,7 +384,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
extern int break_ipl;
template <class Impl>
-Fault
+Fault *
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;
@@ -521,7 +522,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
case ISA::IPR_ITB_PTE_TEMP:
case ISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
case ISA::IPR_HWINT_CLR:
case ISA::IPR_SL_XMIT:
@@ -623,11 +624,11 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
default:
// invalid IPR
- return Unimplemented_Opcode_Fault;
+ return UnimplementedOpcodeFault;
}
// no error...
- return No_Fault;
+ return NoFault;
}
#endif // #if FULL_SYSTEM
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 12:12:50 +0000